摘要
A novel divider based on dual-bit algorithm and its VLSI implementation are presented.Compared with the divider of MIPS microprocessor,it decreases the average executing cycles by 52.5% while its maximum delay is almost the same and its transistor count increases by 60%.Furthermore,the simulation result indicates that the power consumption decreases to 11.3% with the same processing ability.
提出了基于双比特算法的新型除法器及其VLSI实现结构 .与MIPS微处理器中的除法器相比 ,它的平均执行周期减少了 5 2 5 % ,而其最大延时几乎不变 ,仅晶体管数目增加了 6 0 % .仿真结果表明 ,在相同的运算能力下 ,其功耗仅为MIPS中除法器的 11 3% .
基金
国家高技术研究发展计划资助项目 (编号 :2 0 0 2AA1Z10 60 )~~
