一种实现MPEG2传输流码率调整的方法

A Code-rate Adjustment Method for MPEG2 Transport Steam

介绍一种用于MPEG2传输流码率调整的硬件实现方法。首先分析MPEG2的帧格式,然后介绍具体的硬件实现,它是一种基于复杂可编程逻辑器件(CPLD)的码率调整,辅以数字频率合成器(DDS),避免了与信号源时钟的同步问题。同时提供异步串行接口(ASI)和同步并行接口(SPI)输入,并以SPI接口输出。可广泛应用于数字视频传输等各种需要码率调整的场合。

A hardware realization method for MPEG2 transport stream(TS) code-rate adjustment is introduced. First, the frame structure of MPEG2 is analyzed, then the hardware architecture is described. This system is based on CPLD with the addition of DDS, in which the problem about synchronization of the source clock is avoided. TS interfaces ASI and SPI are provided for input and SPI interface for output. This system can widely be used to adjust code-rate for digital video transmission.