面向分模块寄存器传输级结构的高层次综合方法

High Level Synthesis Method for Clustered Register Transfer Level Architecture

随着集成电路工艺技术的发展,连线延时将逐渐主导系统的性能,传统的高层次综合方法已经不能满足设计的需要。文章讨论了寄存器传输级结构对综合方法的影响,并提出使用分模块的寄存器传输级结构作为高层次综合的目标结构。针对新的结构,概括了设计流程,设计了核心算法。实验数据表明,与传统的方法相比,该方法可以有效地改善系统的性能。

When IC technology scaled down to deep submicron range, wire delay gradually dominates circuit performance, traditional high level synthesis methods can no longer meet the requirement for circuit design. The influence of architectures on synthesis methods is discussed, and a clustered register transfer level architecture as object architecture is presented. A new design flow is summarized and a key algorithm is designed for the new architecture. Experimental results demonstrate the efficiency of the new method.