摘要
A new configuration of Bulk-Driven Folded-Cascode (BDFC) amplifier is presented in this paper. Due to this modifying, significant improvement in differential DC-Gain (more than 11 dB) is achieved in compare to the conventional structure. Settling behavior of proposed amplifier is also improved and accuracy more than 8 bit for 500 mV voltage swing is obtained. Simulation results using HSPICE Environment are included which validate the theoretical analysis. The amplifier is designed using standard 0.18 μm CMOS triple-well (level 49) process with supply voltage of 1.2 V. The correct functionality of this configuration is verified from –50℃ to 100℃.
A new configuration of Bulk-Driven Folded-Cascode (BDFC) amplifier is presented in this paper. Due to this modifying, significant improvement in differential DC-Gain (more than 11 dB) is achieved in compare to the conventional structure. Settling behavior of proposed amplifier is also improved and accuracy more than 8 bit for 500 mV voltage swing is obtained. Simulation results using HSPICE Environment are included which validate the theoretical analysis. The amplifier is designed using standard 0.18 μm CMOS triple-well (level 49) process with supply voltage of 1.2 V. The correct functionality of this configuration is verified from –50℃ to 100℃.
