摘要
The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.
The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.
作者
J. Dhurga Devi
J. Dhurga Devi(Department of ECE, College of Engineering, Anna University, Chennai, India)
