摘要
This paper presents the independent source tied photovoltaic (PV) based three-phase three-level diode-clamped-multilevel inverter (DCD-MLI) utilizing field programmable gate array (FPGA) controller. The maximum power point (MPP) is tracked by using fuzzy logic algorithm. Employed for gating signal generation, the space vector modulation (SVM) strategy eradicates the complexity in determining the reference vector location, the ON-time calculations and switching state selection. A digital proportional integral (PI) control algorithm is implemented on a FPGA to keep the current injected into the independent source (grid) sinusoidal and to achieve high dynamic performance with low total harmonic distortion (THD) of output voltage and output current which are 0.97% and 1.26%. With the proposed configuration, the adjustments of modulation index and phase angle are synthesized onto a FPGA by means of hardware description language (VHDL). The efficacy of the scheme is verified through simulation study. To confirm the feasibility of the scheme, experimental studies are carried out on a scaled-down laboratory prototype.
This paper presents the independent source tied photovoltaic (PV) based three-phase three-level diode-clamped-multilevel inverter (DCD-MLI) utilizing field programmable gate array (FPGA) controller. The maximum power point (MPP) is tracked by using fuzzy logic algorithm. Employed for gating signal generation, the space vector modulation (SVM) strategy eradicates the complexity in determining the reference vector location, the ON-time calculations and switching state selection. A digital proportional integral (PI) control algorithm is implemented on a FPGA to keep the current injected into the independent source (grid) sinusoidal and to achieve high dynamic performance with low total harmonic distortion (THD) of output voltage and output current which are 0.97% and 1.26%. With the proposed configuration, the adjustments of modulation index and phase angle are synthesized onto a FPGA by means of hardware description language (VHDL). The efficacy of the scheme is verified through simulation study. To confirm the feasibility of the scheme, experimental studies are carried out on a scaled-down laboratory prototype.
作者
M. Valan Rajkumar
P. Prakasam
P. S. Manoharan
M. Valan Rajkumar;P. Prakasam;P. S. Manoharan(Department of Electrical and Electronics Engineering, Gnanamani College of Technology, Namakkal, India;Department of Electronics and Communication Engineering, United Institute of Technology, Coimbatore, India;Department of Electrical and Electronics Engineering, Thiagarajar College of Engineering, Madurai, India)
