摘要
The integrated circuit (IC) manufacturing process is capital intensive and complex. The production process of unit product (or die, as it is commonly referred to) takes several weeks. Semiconductor factories (fabs) continuously attempt to improve their productivity, as measured in output and cycle time (or mean flow time). The conflicting objective of producing maximum units at minimal production cycle time and at the highest quality, as measured by die yield, is discussed in this paper. The inter-related effects are characterized, and a model is proposed to address this multi-objective function. We then show that, with this model, die cost can be optimized for any given operating conditions of a fab. A numerical example is provided to illustrate the practicality of the model and the proposed optimization method.
The integrated circuit (IC) manufacturing process is capital intensive and complex. The production process of unit product (or die, as it is commonly referred to) takes several weeks. Semiconductor factories (fabs) continuously attempt to improve their productivity, as measured in output and cycle time (or mean flow time). The conflicting objective of producing maximum units at minimal production cycle time and at the highest quality, as measured by die yield, is discussed in this paper. The inter-related effects are characterized, and a model is proposed to address this multi-objective function. We then show that, with this model, die cost can be optimized for any given operating conditions of a fab. A numerical example is provided to illustrate the practicality of the model and the proposed optimization method.
作者
Adar A. Kalir
Adar A. Kalir(Manufacturing Science at Intel Corp., Qiriat-Gat, Israel;Ruppin Academic Center, Ben-Gurion University, Beersheba, Israel)
