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On the Operation of CMOS Active-Cascode Gain Stage

On the Operation of CMOS Active-Cascode Gain Stage
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摘要 An s-domain analysis of the full dynamics of the pole-zero pair (frequency doublet) associated with the broadly used CMOS active-cascode gain-enhancement technique is presented. Quantitative results show that three scenarios can arise for the settling behavior of a closed-loop active-cascode operational amplifier depending on the relative locations of the unity-gain frequencies of the auxiliary and the main amplifiers. The analysis also reveals that, although theoretically possible, it is practically difficult to achieve an exact pole-zero cancellation. The analytical results presented here provide theoretical guidelines to the design of CMOS operational amplifiers using this technique. An s-domain analysis of the full dynamics of the pole-zero pair (frequency doublet) associated with the broadly used CMOS active-cascode gain-enhancement technique is presented. Quantitative results show that three scenarios can arise for the settling behavior of a closed-loop active-cascode operational amplifier depending on the relative locations of the unity-gain frequencies of the auxiliary and the main amplifiers. The analysis also reveals that, although theoretically possible, it is practically difficult to achieve an exact pole-zero cancellation. The analytical results presented here provide theoretical guidelines to the design of CMOS operational amplifiers using this technique.
作者 Yun Chiu
出处 《Journal of Computer and Communications》 2013年第6期18-24,共7页 电脑和通信(英文)
关键词 CMOS Operational Amplifier GAIN Enhancement ACTIVE CASCODE Regulated CASCODE GAIN Boosting Pole- Zero Pair DOUBLET Slow SETTLING CMOS Operational Amplifier Gain Enhancement Active Cascode Regulated Cascode Gain Boosting Pole- Zero Pair Doublet Slow Settling
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