摘要
This paper reports design of a CMOS optical receiver front-end using 0.18 μm technology. Design process is current associated with photodiode using trans-impedance amplifier (TIA) for wide bandwidth, high gain, low input referred noise and wide dynamic range. The Automated Gain Control (AGC) voltage is used to provide variable gain for multilevel signals. This design is simulated in 0.18 μm UMC technology for the performance analysis. The best simulation results are reported the maximum TIA gain of 67.26 dB? at 0 V AGC followed by a post amplifier gain of 86.70 dB?. The bandwidth range is 7.03 GHz to 11.5 GHz corresponding to 0 - 3 V AGC respectively. The input referred noise level value is 43.86 pA/√Hz up to 10 GHz frequency. In addition authors have obtained the common mode rejection ratio (CMRR) is 72.42 dB and rectified group delay is 144.48 ps. Verification of the design, reported results are compared with earlier published work and improvements obtained in the present results.
This paper reports design of a CMOS optical receiver front-end using 0.18 μm technology. Design process is current associated with photodiode using trans-impedance amplifier (TIA) for wide bandwidth, high gain, low input referred noise and wide dynamic range. The Automated Gain Control (AGC) voltage is used to provide variable gain for multilevel signals. This design is simulated in 0.18 μm UMC technology for the performance analysis. The best simulation results are reported the maximum TIA gain of 67.26 dB? at 0 V AGC followed by a post amplifier gain of 86.70 dB?. The bandwidth range is 7.03 GHz to 11.5 GHz corresponding to 0 - 3 V AGC respectively. The input referred noise level value is 43.86 pA/√Hz up to 10 GHz frequency. In addition authors have obtained the common mode rejection ratio (CMRR) is 72.42 dB and rectified group delay is 144.48 ps. Verification of the design, reported results are compared with earlier published work and improvements obtained in the present results.
