8Premkishore Shivakumar,Michael Kistler,Stephen W Keckler,et al.Modeling the effect of technology trends on the soft error rate of combinational logic[C].2002 Int'l Conf on Dependable Systems and Networks,Bethesda,USA,2002
9P P Shirvani,E J McCluskey.PADded cache:A new fault tolerance technique for cache memories[C].IEEE 17th VLSI Test Symposium,San Diego,1999
10M Rebaudengo,M Sonza Reorda,M Violante.An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor[C].Design Automation and Test in Europe Conference and Exhibition,Munich,Germany,2003