A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopt...A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.展开更多
An IF-sampling S/H is presented,which adopts a flip-around structure,bottom-plate sampling technique and improved input bootstrapped switches.To achieve high sampling linearity over a wide input frequency range,the fl...An IF-sampling S/H is presented,which adopts a flip-around structure,bottom-plate sampling technique and improved input bootstrapped switches.To achieve high sampling linearity over a wide input frequency range,the floating well technique is utilized to optimize the input switches.Besides,techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance.The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit,250 MS/s pipeline ADC.For30 MHz input,the measured SFDR/SNDR of the ADC is 94.7 dB/68.5dB,which can remain over 84.3 dB/65.4dB for input frequency up to 400 MHz.The ADC presents excellent dynamic performance at high input frequency,which is mainly attributed to the parasitics optimized S/H circuit.展开更多
This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter（ADC）.The algorithm does not modify the analog circuit of pipelined stages and cal...This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter（ADC）.The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic.Based on the analysis of the output codes,the calibration logic estimates the bit weight of each stage and corrects the outputs.An experimental 14-bit pipelined ADC is fabricated to verify the algorithm.The results show that INL errors drop from 20 LSB to 1.7 LSB,DNL errors drop from 2 LSB to 0.4 LSB,SNDR grows from 57 to 65.7 dB and THD drops from -58 to -81 dB.The linearity of the pipelined ADC is improved significantly.展开更多
基金supported by the National High Technology Research and Development Program of China(No.2006AA04A109)
文摘A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.
基金supported by the Shenzhen Project(No.JSGG20150512162029307)
文摘An IF-sampling S/H is presented,which adopts a flip-around structure,bottom-plate sampling technique and improved input bootstrapped switches.To achieve high sampling linearity over a wide input frequency range,the floating well technique is utilized to optimize the input switches.Besides,techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance.The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit,250 MS/s pipeline ADC.For30 MHz input,the measured SFDR/SNDR of the ADC is 94.7 dB/68.5dB,which can remain over 84.3 dB/65.4dB for input frequency up to 400 MHz.The ADC presents excellent dynamic performance at high input frequency,which is mainly attributed to the parasitics optimized S/H circuit.
文摘This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter（ADC）.The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic.Based on the analysis of the output codes,the calibration logic estimates the bit weight of each stage and corrects the outputs.An experimental 14-bit pipelined ADC is fabricated to verify the algorithm.The results show that INL errors drop from 20 LSB to 1.7 LSB,DNL errors drop from 2 LSB to 0.4 LSB,SNDR grows from 57 to 65.7 dB and THD drops from -58 to -81 dB.The linearity of the pipelined ADC is improved significantly.
