In this paper, the concept of φ-mapping and some fixed point theorems for such mappings are introduced and presented. These theorems extend corresponding theorems in metric space.
Parity testing is one of the compact testing techniques, which, traditionally, relies on applying all 2^n input combinations to an n-input combinational circuit without need of knowing the implementation of the circui...Parity testing is one of the compact testing techniques, which, traditionally, relies on applying all 2^n input combinations to an n-input combinational circuit without need of knowing the implementation of the circuits under test. The faults can be detected just by observing and comparing its parity of whole output of circuit with the expectation one. The way seemed to be less interesting to the test eagineers in the past days, mainly due to the reasons of its exhaustive testing and time-cousuming, which became a barrier as the number of input lines gets growing. However its great facility and convenience in testing still interest to the engineers who need to have a quick look at the qualities of the circuits without generating the test patterns for a given circuit to be tested. In this paper, a new approach called pseudo-parity testing is presented to deal with the dilemma we are facing： i. e. to change an exhaustive parity testing into a non-exhaustive one, followed by a pseudo- parity testable design to help realize the new way of pseudo-parity testing. The idea of pseudo-parity testing presented in this paper may resume its spirits towards its promising future.展开更多
文摘In this paper, the concept of φ-mapping and some fixed point theorems for such mappings are introduced and presented. These theorems extend corresponding theorems in metric space.
基金This work was supported by National Natural Science Foundation of China under the grant No .60173029 and 60473033
文摘Parity testing is one of the compact testing techniques, which, traditionally, relies on applying all 2^n input combinations to an n-input combinational circuit without need of knowing the implementation of the circuits under test. The faults can be detected just by observing and comparing its parity of whole output of circuit with the expectation one. The way seemed to be less interesting to the test eagineers in the past days, mainly due to the reasons of its exhaustive testing and time-cousuming, which became a barrier as the number of input lines gets growing. However its great facility and convenience in testing still interest to the engineers who need to have a quick look at the qualities of the circuits without generating the test patterns for a given circuit to be tested. In this paper, a new approach called pseudo-parity testing is presented to deal with the dilemma we are facing： i. e. to change an exhaustive parity testing into a non-exhaustive one, followed by a pseudo- parity testable design to help realize the new way of pseudo-parity testing. The idea of pseudo-parity testing presented in this paper may resume its spirits towards its promising future.
