CMOS毫米波低功耗超宽带共栅低噪声放大器（英文）

陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器（LNA）.该LNA用标准90-nm RFCMOS工艺实现并具有如下特征：在28.5～39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27～42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数（NF）为4.2dB,平均NF在27 ～ 42 GHz频段内为5.1 dB;S11在整个测试频段内小于-11 dB.40 GHz处输入三阶交调点（IIP3）的测试值为＋2 dBm.整个电路的直流功耗为5.3 mW.包括焊盘在内的芯片面积为0.58 mm×0.48 mm。

戴胜繁殖习性的观察研究

戴胜(Upupa epops Linneus)隶属于佛法僧目的一种中型食虫鸟类,广泛分布在全国,有三个亚种,在黑龙江省分布的为普通亚种(Upupa epopsepops)。为夏候鸟,3月下旬迁来,4月中旬开始繁殖,9月初开始向越冬地迁徙。一,产卵及孵化戴胜刚迁来时常以单个活动。4月初开始配对,雌雄互相追逐并发出“ga-、ga-”的鸣声。雄鸟常为争夺配偶而打斗,不断“ga,ga”地鸣叫。

兴凯湖自然保护区鱼类两栖爬行动物资源

保护区有圆口纲动物一科一种;鱼纲12科48种;两栖纲动物4科6种;爬行纲3科6种。

Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.

A Ka-band wide locking range frequency divider with high injection sensitivity

This paper proposes a direct injection-locked frequency divider（ILFD） with a wide locking range in the Ka-band. A complementary cross-coupled architecture is used to enhance the overdriving voltage of the switch transistor so that the divider locking range is extended efficiently. New insights into the locking range and output power are proposed. A new method to analyze and optimize the injection sensitivity is presented and a layout technique to reduce the parasitics of the cross-coupled transistors is applied to decrease the frequency shift and the locking range degradation. The circuit is designed in a standard 90-nm CMOS process. The total locking range of the ILFD is 43.8% at 34.5 GHz with an incident power of –3.5 dBm. The divider IC consumes 3.6 mW of power at the supply voltage of 1.2 V. The chip area including the pads is 0.50.5 mm2.

IC design of low power, wide tuning range VCO in 90 nm CMOS technology

A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET（IMOS） varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range（FTR） of 18.4%and a phase noise of –101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.

A 31.7-GHz high linearity millimeter-wave CMOS LNA using an ultra-wideband input matching technique

A CMOS low-noise amplifier （LNA） operating at 31.7 GHz with a low input return loss （S11） and high linearity is proposed. The wideband input matching was achieved by employing a simple LC compounded network to generate more than one S11 dip below -10 dB level. The principle of the matching circuit is analyzed and the critical factors with significant effect on the input impedance （Zin） are determined. The relationship between the input impedance and the load configuration is explored in depth, which is seldom concentrated upon previously. In addition, the noise of the input stage is modeled using a cascading matrix instead of conventional noise theory. In this way Zin and the noise figure can be calculated using one uniform formula. The linearity analysis is also performed in this paper. Finally, an LNA was designed for demonstration purposes. The measurement results show that the proposed LNA achieves a maximum power gain of 9.7 dB and an input return loss of 〈 -10 dB from 29 GHz to an elevated frequency limited by the measuring range. The measured input-referred compression point and the third order inter-modulation point are -7.8 and 5.8 dBm, respectively. The LNA is fabricated in a 90-nm RF CMOS process and occupies an area of 755 × 670μm2 including pads. The whole circuit dissipates a DC power of 24 mW from one 1.3-V supply.

A 3.16–7 GHz transformer-based dual-band CMOS VCO

A dual-band, wide tuning range voltage-controlled oscillator that uses transformer-based fourth-order（LC） resonator with a compact common-centric layout is presented. Compared with the traditional wide band（VCO）, it can double frequency tuning range without degrading phase noise performance. The relationship between the coupling coefficient of the transformer, selection of frequency bands, and the quality factor at each band is investigated. The transformer used in the resonator is a circular asymmetric concentric topology. Compared with conventional octagon spirals, the proposed circular asymmetric concentric transformer results in a higher qualityfactor, and hence a lower oscillator phase noise. The VCO is designed and fabricated in a 0.18- m CMOS technology and has 75% wide tuning range of 3.16–7.01 GHz. Depending on the oscillation frequency, the VCO current consumption is adjusted from 4.9 to 6.3 m A. The measured phase noises at 1 MHz offset from carrier frequencies of 3.1, 4.5, 5.1, and 6.6 GHz are –122.5, –113.3, –110.1, and –116.8 d Bc/Hz, respectively. The chip area, including the pads, is 1.2×0.62 mm^2 and the supply voltage is 1.8 V.