A novel low temperature poly\|Si(LTPS) ultra\|thin channel thin film transistor (UTC\|TFT) technology is proposed. The UTC\|TFT has an ultra\|thin channel region (30nm) and a thick drain/source region (300nm). The ult...A novel low temperature poly\|Si(LTPS) ultra\|thin channel thin film transistor (UTC\|TFT) technology is proposed. The UTC\|TFT has an ultra\|thin channel region (30nm) and a thick drain/source region (300nm). The ultra\|thin channel region that can result in a lower grain\|boundary trap density in the channel is connected to the heavily\|doped thick drain/source region through a lightly\|doped overlapped region. The overlapped lightly\|doped region provides an effective way for the electric field to spread in the channel near the drain at high drain biases, thereby reducing the electric field there significantly. Simulation results show the UTC\|TFT experiences a 50% reduction in peak lateral electric field compared to that of the conventional TFT. With the low grain\|boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are achieved in the UTC\|TFT. Moreover, this technology provides the complementary LTPS\|TFTs with more than 2 times increase in on\|current, 3.5 times reduction in off\|current compared to the conventional thick channel LTPS TFTs.展开更多
为了限制地震与风对建筑物造成的损坏,估算建筑物的侧向变形已成为建筑结构设计的重要内容.尽管有些国家的建筑规范中已给出了估算木结构剪力墙侧向变形的方法,但这些方法并不适用于无抗倾覆锚固件木结构剪力墙.在Forintek钉节点试验结...为了限制地震与风对建筑物造成的损坏,估算建筑物的侧向变形已成为建筑结构设计的重要内容.尽管有些国家的建筑规范中已给出了估算木结构剪力墙侧向变形的方法,但这些方法并不适用于无抗倾覆锚固件木结构剪力墙.在Forintek钉节点试验结果的基础上,建议一个新的钉节点——侧向荷载—变形公式,并将美国《统一建筑规范》(Uniform Building Code)所采用的四项式变形公式进行了扩展,给出能进行无抗倾覆锚固件木结构剪力墙侧向变形计算的公式.计算预测值与试验结果对比较好.展开更多
A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,ie.,it does not contain any critical photolithographic steps.The nano-s...A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,ie.,it does not contain any critical photolithographic steps.The nano-scale masking pattern for gate formation is formed according to the image transfer of an edge-defined spacer.Experimental results reveal that the resultant gate length,about 75 to 85 percent of the thickness,is determined by the thickness of the film to form the spacer.From SEM photograph,the cross-section of the poly-Si gate is seen to be an inverted-trapezoid,which is useful to reduce the gate resistance.展开更多
文摘A novel low temperature poly\|Si(LTPS) ultra\|thin channel thin film transistor (UTC\|TFT) technology is proposed. The UTC\|TFT has an ultra\|thin channel region (30nm) and a thick drain/source region (300nm). The ultra\|thin channel region that can result in a lower grain\|boundary trap density in the channel is connected to the heavily\|doped thick drain/source region through a lightly\|doped overlapped region. The overlapped lightly\|doped region provides an effective way for the electric field to spread in the channel near the drain at high drain biases, thereby reducing the electric field there significantly. Simulation results show the UTC\|TFT experiences a 50% reduction in peak lateral electric field compared to that of the conventional TFT. With the low grain\|boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are achieved in the UTC\|TFT. Moreover, this technology provides the complementary LTPS\|TFTs with more than 2 times increase in on\|current, 3.5 times reduction in off\|current compared to the conventional thick channel LTPS TFTs.
文摘为了限制地震与风对建筑物造成的损坏,估算建筑物的侧向变形已成为建筑结构设计的重要内容.尽管有些国家的建筑规范中已给出了估算木结构剪力墙侧向变形的方法,但这些方法并不适用于无抗倾覆锚固件木结构剪力墙.在Forintek钉节点试验结果的基础上,建议一个新的钉节点——侧向荷载—变形公式,并将美国《统一建筑规范》(Uniform Building Code)所采用的四项式变形公式进行了扩展,给出能进行无抗倾覆锚固件木结构剪力墙侧向变形计算的公式.计算预测值与试验结果对比较好.
文摘A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,ie.,it does not contain any critical photolithographic steps.The nano-scale masking pattern for gate formation is formed according to the image transfer of an edge-defined spacer.Experimental results reveal that the resultant gate length,about 75 to 85 percent of the thickness,is determined by the thickness of the film to form the spacer.From SEM photograph,the cross-section of the poly-Si gate is seen to be an inverted-trapezoid,which is useful to reduce the gate resistance.
