Gate-grounded N-channel MOSFET(GGNMOS)has been extensively used for on-chip electrostatic discharge(ESD)protection.However,the ESD performance of the conventional GGNMOS is significantly degraded by the current crowdi...Gate-grounded N-channel MOSFET(GGNMOS)has been extensively used for on-chip electrostatic discharge(ESD)protection.However,the ESD performance of the conventional GGNMOS is significantly degraded by the current crowding effect.In this paper,an enhanced GGNMOS with P-base layer(PB-NMOS)are proposed to improve the ESD robustness in BCD process without the increase in layout area or additional layer.TCAD simulations are carried out to explain the underlying mechanisms of that utilizing the P-base layer can effectively restrain the current crowing effect in proposed devices.All devices are fabricated in a 0.5-μm BCD process and measured using the transmission line pulsing(TLP)tester.Compared with the conventional GGNMOS,the proposed PB-NMOS devices offer a higher failure current than its conventional counterpart,which can be increased by 15.38%.Furthermore,the PB-NMOS type 3 possesses a considerably lower trigger voltage than the conventional GGNMOS to protect core circuit effectively.展开更多
A robust electron device called the enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) for electrostatic discharge (ESD) protection applications has been proposed and implemented in a 0.18-μm 5-V/2...A robust electron device called the enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) for electrostatic discharge (ESD) protection applications has been proposed and implemented in a 0.18-μm 5-V/24-V BCD process. The proposed EGDTSCR is constructed by adding two gated diodes into a conventional ESD device called the modified lateral silicon-controlled rectifier (MLSCR). With the shunting effect of the surface gated diode path, the proposed EGDTSCR, with a width of 50 μm, exhibits a higher failure current (i.e., 3.82 A) as well as a higher holding voltage (i.e., 10.21 V) than the MLSCR.展开更多
Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,eas...Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.展开更多
文摘Gate-grounded N-channel MOSFET(GGNMOS)has been extensively used for on-chip electrostatic discharge(ESD)protection.However,the ESD performance of the conventional GGNMOS is significantly degraded by the current crowding effect.In this paper,an enhanced GGNMOS with P-base layer(PB-NMOS)are proposed to improve the ESD robustness in BCD process without the increase in layout area or additional layer.TCAD simulations are carried out to explain the underlying mechanisms of that utilizing the P-base layer can effectively restrain the current crowing effect in proposed devices.All devices are fabricated in a 0.5-μm BCD process and measured using the transmission line pulsing(TLP)tester.Compared with the conventional GGNMOS,the proposed PB-NMOS devices offer a higher failure current than its conventional counterpart,which can be increased by 15.38%.Furthermore,the PB-NMOS type 3 possesses a considerably lower trigger voltage than the conventional GGNMOS to protect core circuit effectively.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61874098 and 61974017)the Fundamental Research Project for Central Universities,China(Grant No.ZYGX2018J025).
文摘A robust electron device called the enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) for electrostatic discharge (ESD) protection applications has been proposed and implemented in a 0.18-μm 5-V/24-V BCD process. The proposed EGDTSCR is constructed by adding two gated diodes into a conventional ESD device called the modified lateral silicon-controlled rectifier (MLSCR). With the shunting effect of the surface gated diode path, the proposed EGDTSCR, with a width of 50 μm, exhibits a higher failure current (i.e., 3.82 A) as well as a higher holding voltage (i.e., 10.21 V) than the MLSCR.
基金Project supported by the National Natural Science Foundation of China(Grant No.61974017)。
文摘Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.
