s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure re...s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure reduces the propagation delay and has higher operating speed.Based on this structure,an im proved D- flip- flop(DFF) using dynam ic circuit technique is proposed.A prototype is fabricated and the measured results show that this prescaler works well in gigahertz frequency range and consumes only35 m W(including three power- hungry output buffers) when the input frequency is2 .5 GHz and the power supply voltage is2 .5 V.Due to its excellent perform ance,the prescaler could be applied to many RF system s.展开更多
A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and sin...A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and single-ended to differential conversion.The mixers are implemented in 0.18μm CMOS process.The measured results are given to show their performance.展开更多
A voltage controlled oscillator (VCO) which can generate 2 4GHz quadrature local oscillating (LO) signals is reported.It combines a LC VCO,realized by on chip symmetrical spiral inductors and differential diodes,an...A voltage controlled oscillator (VCO) which can generate 2 4GHz quadrature local oscillating (LO) signals is reported.It combines a LC VCO,realized by on chip symmetrical spiral inductors and differential diodes,and a two stage ring VCO.The principle of this VCO is demonstrated and further the phase noise is discussed in detail.The fabrication of prototype is demonstrated using 0 25μm single poly five metal N well salicide CMOS digital process.The reports show that the novel VCO is can generate quadrature LO signals with a tuning range of more than 300MHz as well as the phase noise--104 33dBc/Hz at 600KHz offset at 2 41GHz (when measuring only one port of differential outputs).In addition,this VCO can work in low power supply voltage and dissipate low power,thus it can be used in many integrated transceivers.展开更多
An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are b...An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.展开更多
A low phase noise quadrature oscillator using the new injection locked technique is proposed. The incident signal is directly injected into the common-source connection of the sub-harmonic oscillator. In principle, th...A low phase noise quadrature oscillator using the new injection locked technique is proposed. The incident signal is directly injected into the common-source connection of the sub-harmonic oscillator. In principle, the phase noise performance of the quadrature output is better than the sub-harmonic oscillator itself. The quadrature oscillator is implemented in a 0. 25μm CMOS process. Measurements show the proposed oscillator could achieve a phase noise of --130dBc/Hz at 1MHz offset from 1. 13GHz carrier while only drawing an 8.0mA current from the 2.5V power supply.展开更多
A 2. 4GHz CMOS monolithic transceiver front-end for IEEE 802. llb wireless LAN applications is presented. The receiver and transmitter are both of superheterodyne structure for good system performance. The frontend co...A 2. 4GHz CMOS monolithic transceiver front-end for IEEE 802. llb wireless LAN applications is presented. The receiver and transmitter are both of superheterodyne structure for good system performance. The frontend consists of five blocks., low noise amplifier,down-converter, up-converter, pre-amplifier, and LO buffer. Their input/output impedance are all on-chip matched to 50 Ω except the down-converter which has open-drain outputs. The transceiver RF front-end has been implemented in a 0. 18μm CMOS process. When the LNA and the down-converter are directly connected, the measured noise figure is 5.2dB, the measured available power gain 12. 5dB, the input l dB compression point --18dBm,and the third-order input intercept point --7dBm. The receiver front-end draws 13.6mA currents from the 1.8V power supply. When the up-converter and pre-amplifier are directly connected, the measured noise figure is 12.4dB, the power gain is 23. 8dB, the output ldB compression point is 1.5dBm, and the third-order output intercept point is 16dBm. The transmitter consumes 27.6mA current from the 1.8V power supply.展开更多
A novel general purpose sense amplifier based flip flop is proposed.Compared to other flip flops,the proposed flip flop has faster operating speed under the approximately same power consumption,and needs fewer tr...A novel general purpose sense amplifier based flip flop is proposed.Compared to other flip flops,the proposed flip flop has faster operating speed under the approximately same power consumption,and needs fewer transistors and consumes smaller area.Moreover,it eliminates the glitch problem.By using pseudo PMOS dynamic technique,its performance is further improved.展开更多
An improved high-resolution current-mode sorter is presented.Its structure complexity is O(N),which is crucial to the expansion of its size,and its dynamic range is large.Only one clock signal and one reset signal are...An improved high-resolution current-mode sorter is presented.Its structure complexity is O(N),which is crucial to the expansion of its size,and its dynamic range is large.Only one clock signal and one reset signal are needed.No biasing signal is required.The operation point is constructed according to the input current,so it is self-adaptive,which is very important for an all-purpose component.In average value circuit,subtraction circuit,Winner-Take-All(WTA) circuit and control circuit,it has good performance even at a large input current.This sorter has high precision,high resolution and low power,as has been proved via HSPICE simulation.It can be implemented in the standard digital CMOS technology and widely used in many fields,so it is of great value in applications.展开更多
The design and implementation of a CMOS LC VCO with 3. 2-6. 1GHz tuning range are presented. This is achieved by enhancing the tuning capability of the binary-weighted band-switching MIM capacitor. The circuit has bee...The design and implementation of a CMOS LC VCO with 3. 2-6. 1GHz tuning range are presented. This is achieved by enhancing the tuning capability of the binary-weighted band-switching MIM capacitor. The circuit has been implemented in a 0. 18μm RF/Mixed-Signal CMOS process. The measured phase noise is - 101.67dBc/Hz at 1MHz offset from a 5.5GHz carrier,and the VCO core draws 9.69mA current from a 1.8V supply.展开更多
Based on a physical understanding of nonlinearity and mismatch, a novel offset-cancellation technique for low voltage CMOS differential amplifiers is proposed. The technique transfers the offset voltage from the outpu...Based on a physical understanding of nonlinearity and mismatch, a novel offset-cancellation technique for low voltage CMOS differential amplifiers is proposed. The technique transfers the offset voltage from the output to other parts of the differential amplifier and can greatly reduce the input-referred offset voltage without extra power consumption. A 1.8V CMOS differential amplifier is implemented in 0.18μm CMOS process using the proposed technique. The simulation results show that the technique could reduce the input-referred offset voltage of the amplifier by 40% with a 20% load transistor mismatch and a 10% input differential transistor mismatch. Moreover, the proposed technique consumes the least power and achieves the highest integration among various offset-cancellation techniques.展开更多
文摘s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure reduces the propagation delay and has higher operating speed.Based on this structure,an im proved D- flip- flop(DFF) using dynam ic circuit technique is proposed.A prototype is fabricated and the measured results show that this prescaler works well in gigahertz frequency range and consumes only35 m W(including three power- hungry output buffers) when the input frequency is2 .5 GHz and the power supply voltage is2 .5 V.Due to its excellent perform ance,the prescaler could be applied to many RF system s.
文摘A down-conversion mixer and an up-conversion mixer for 2.4GHz WLAN transceivers are presented.The down-conversion mixer uses a class-AB input stage to get high linearity and to realize input impedance matching and single-ended to differential conversion.The mixers are implemented in 0.18μm CMOS process.The measured results are given to show their performance.
文摘A voltage controlled oscillator (VCO) which can generate 2 4GHz quadrature local oscillating (LO) signals is reported.It combines a LC VCO,realized by on chip symmetrical spiral inductors and differential diodes,and a two stage ring VCO.The principle of this VCO is demonstrated and further the phase noise is discussed in detail.The fabrication of prototype is demonstrated using 0 25μm single poly five metal N well salicide CMOS digital process.The reports show that the novel VCO is can generate quadrature LO signals with a tuning range of more than 300MHz as well as the phase noise--104 33dBc/Hz at 600KHz offset at 2 41GHz (when measuring only one port of differential outputs).In addition,this VCO can work in low power supply voltage and dissipate low power,thus it can be used in many integrated transceivers.
文摘An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.
文摘A low phase noise quadrature oscillator using the new injection locked technique is proposed. The incident signal is directly injected into the common-source connection of the sub-harmonic oscillator. In principle, the phase noise performance of the quadrature output is better than the sub-harmonic oscillator itself. The quadrature oscillator is implemented in a 0. 25μm CMOS process. Measurements show the proposed oscillator could achieve a phase noise of --130dBc/Hz at 1MHz offset from 1. 13GHz carrier while only drawing an 8.0mA current from the 2.5V power supply.
文摘A 2. 4GHz CMOS monolithic transceiver front-end for IEEE 802. llb wireless LAN applications is presented. The receiver and transmitter are both of superheterodyne structure for good system performance. The frontend consists of five blocks., low noise amplifier,down-converter, up-converter, pre-amplifier, and LO buffer. Their input/output impedance are all on-chip matched to 50 Ω except the down-converter which has open-drain outputs. The transceiver RF front-end has been implemented in a 0. 18μm CMOS process. When the LNA and the down-converter are directly connected, the measured noise figure is 5.2dB, the measured available power gain 12. 5dB, the input l dB compression point --18dBm,and the third-order input intercept point --7dBm. The receiver front-end draws 13.6mA currents from the 1.8V power supply. When the up-converter and pre-amplifier are directly connected, the measured noise figure is 12.4dB, the power gain is 23. 8dB, the output ldB compression point is 1.5dBm, and the third-order output intercept point is 16dBm. The transmitter consumes 27.6mA current from the 1.8V power supply.
文摘A novel general purpose sense amplifier based flip flop is proposed.Compared to other flip flops,the proposed flip flop has faster operating speed under the approximately same power consumption,and needs fewer transistors and consumes smaller area.Moreover,it eliminates the glitch problem.By using pseudo PMOS dynamic technique,its performance is further improved.
文摘An improved high-resolution current-mode sorter is presented.Its structure complexity is O(N),which is crucial to the expansion of its size,and its dynamic range is large.Only one clock signal and one reset signal are needed.No biasing signal is required.The operation point is constructed according to the input current,so it is self-adaptive,which is very important for an all-purpose component.In average value circuit,subtraction circuit,Winner-Take-All(WTA) circuit and control circuit,it has good performance even at a large input current.This sorter has high precision,high resolution and low power,as has been proved via HSPICE simulation.It can be implemented in the standard digital CMOS technology and widely used in many fields,so it is of great value in applications.
文摘The design and implementation of a CMOS LC VCO with 3. 2-6. 1GHz tuning range are presented. This is achieved by enhancing the tuning capability of the binary-weighted band-switching MIM capacitor. The circuit has been implemented in a 0. 18μm RF/Mixed-Signal CMOS process. The measured phase noise is - 101.67dBc/Hz at 1MHz offset from a 5.5GHz carrier,and the VCO core draws 9.69mA current from a 1.8V supply.
文摘Based on a physical understanding of nonlinearity and mismatch, a novel offset-cancellation technique for low voltage CMOS differential amplifiers is proposed. The technique transfers the offset voltage from the output to other parts of the differential amplifier and can greatly reduce the input-referred offset voltage without extra power consumption. A 1.8V CMOS differential amplifier is implemented in 0.18μm CMOS process using the proposed technique. The simulation results show that the technique could reduce the input-referred offset voltage of the amplifier by 40% with a 20% load transistor mismatch and a 10% input differential transistor mismatch. Moreover, the proposed technique consumes the least power and achieves the highest integration among various offset-cancellation techniques.
