With the device feature's size miniaturization in very large scale integrated circuit and ultralarge scale integrated circuit towards the sub\|micron and beyond level, the next generation of IC device requires s...With the device feature's size miniaturization in very large scale integrated circuit and ultralarge scale integrated circuit towards the sub\|micron and beyond level, the next generation of IC device requires silicon wafers with more improved electrical characteristics and reliability as well as a high perfection of the wafer surface. Compared with the polished wafer with a relatively high density of crystal originated defects (e. g. COPs), silicon epi\|wafers can meet such high requirements. The current development of researches on the 150mm silicon epi\|wafers for advanced IC applications is described. The P/P\++ CMOS silicon epi\|wafers were fabricated on a PE2061 Epitaxial Reactor (made by Italian LPE Company). The material parameters of epi\|wafers, such as epi\|defects, uniformity of thickness and resistivity, transition width, and minority carrier generation lifetime for epi\|layer were characterized in detail. It is demonstrated that the 150mm silicon epi\|wafers on PE2061 can meet the stringent requirements for the advanced IC applications.展开更多
The increasing emphasis on the sub\|micron CMOS/SOS devices has placed a demand for high quality thin silicon on sapphire (SOS) films with thickness of the order 100-200nm. It is demonstrated that the crystalline qua...The increasing emphasis on the sub\|micron CMOS/SOS devices has placed a demand for high quality thin silicon on sapphire (SOS) films with thickness of the order 100-200nm. It is demonstrated that the crystalline quality of as\|grown thin SOS films by chemically vapor deposition method can be greatly improved by solid phase epitaxy (SPE) process: implantation of self\|silicon ions and subsequent thermal annealing. Subsequent regrowth of this amorphous layer leads to a great improvement in silicon layer crystallinity and channel carrier mobility, respectively by double crystal X\|ray diffraction and electrical measurements. Thin SPE SOS films would have application to the high\|performance CMOS circuitry.展开更多
基金Project Supported by National Ninth5-year Plan of China.
文摘With the device feature's size miniaturization in very large scale integrated circuit and ultralarge scale integrated circuit towards the sub\|micron and beyond level, the next generation of IC device requires silicon wafers with more improved electrical characteristics and reliability as well as a high perfection of the wafer surface. Compared with the polished wafer with a relatively high density of crystal originated defects (e. g. COPs), silicon epi\|wafers can meet such high requirements. The current development of researches on the 150mm silicon epi\|wafers for advanced IC applications is described. The P/P\++ CMOS silicon epi\|wafers were fabricated on a PE2061 Epitaxial Reactor (made by Italian LPE Company). The material parameters of epi\|wafers, such as epi\|defects, uniformity of thickness and resistivity, transition width, and minority carrier generation lifetime for epi\|layer were characterized in detail. It is demonstrated that the 150mm silicon epi\|wafers on PE2061 can meet the stringent requirements for the advanced IC applications.
文摘The increasing emphasis on the sub\|micron CMOS/SOS devices has placed a demand for high quality thin silicon on sapphire (SOS) films with thickness of the order 100-200nm. It is demonstrated that the crystalline quality of as\|grown thin SOS films by chemically vapor deposition method can be greatly improved by solid phase epitaxy (SPE) process: implantation of self\|silicon ions and subsequent thermal annealing. Subsequent regrowth of this amorphous layer leads to a great improvement in silicon layer crystallinity and channel carrier mobility, respectively by double crystal X\|ray diffraction and electrical measurements. Thin SPE SOS films would have application to the high\|performance CMOS circuitry.
