基于动态监测工作的森林资源管理问题研究

森林资源在我国生态资源中属于重要内容,通过采取动态监测方法,可以清楚了解森林资源现状,科学划定生态保护红线,对保护国土生态环境具有促进作用。在森林资源管理过程中采取动态监测方法,可以更好了解森林资源变化情况,便于采取有效措施推动我国林业的可持续发展。本文通过分析森林资源动态监测的重要性及有待解决的问题,提出了基于动态监测工作的森林资源管理策略。

浙江特色小镇发展症结与路径规划——以18个特色小镇为例

通过对典型抽样抽取出的18个特色小镇的实地调研,文章创新性地提出从"产业发展、功能叠加、建设形态、制度供给"四个维度来评价特色小镇,在雷达图确定的三大发展模式和熵值法综合评价的基础上,文章针对浙江省特色小镇建设过程中存在的共性和特性问题,提出了具有浙江特色的普适性"四维联动"发展路径规划。针对某个具体的小镇,得分较低的维度是该小镇发展的薄弱之处,可以借鉴普适性的路径,对症下药,并根据小镇的实际情况,因地制宜,采取更细化更具体的建议。

复合沟道氟离子增强型AlGaN/GaN HEMT的研究

提出一种复合沟道氟离子(F-)增强型AlGaN/GaN HEMT(Hybrid-channel enhancement-mode AlGaN/GaN HEMT,HCE-HEMT)新结构。该结构引入高、低浓度F-复合沟道,其中高浓度F-注入区位于沟道靠近源漏两端以调制阈值电压,获得增强型器件;低浓度F-区位于沟道中部以调制肖特基栅电极的正向开启电压,增加器件承受的栅电压摆幅,但它对其下方二维电子气的耗尽作用很弱。同时,高浓度区只占栅长的40%,减轻高浓度F-对沟道的影响,提升器件的电流能力。利用Sentaurus软件仿真,结果显示,与传统F-增强型AlGaN/GaN HEMT相比,HCE-HEMT载流能力提高了40.3%,比导通电阻下降了23.3%,同时反向耐压仅下降了5.3%。

基于河道生态基流保障的农田生态系统服务价值损失量研究

河道生态基流保障的经济损失量直接决定着政府部门对生态基流保障的决策,同时也为河道生态基流的合理保障水平提供定量依据。基于河道生态基流保障的粮食损失引起的农田生态系统服务价值损失,提出了河道生态基流保障的农田生态系统服务价值损失量的计算方法,探讨了农田生态系统服务价值损失量的变化规律,并分析了价值损失量处理办法以及粮食市场价值对其影响变化。研究表明:来水量是计算农田生态系统服务价值损失量的基础,来水量年内分配影响农田生态系统服务价值损失量;通过水权交易和生态补偿等两种方法对河道生态基流保障的经济损失量进行处理,有利于促进农田生态系统和河道生态基流保障的协调发展;同时,粮食市场价格变化也会引起农田生态系统服务价值损失量变化。

海绵城市低影响开发措施应用的风险研究

海绵城市建设是近年来城市雨洪管理方面的热点话题,经过几年的建设发展,多个试点城市已经进入考核评估阶段。回顾了透水铺装、雨水花园、绿色屋顶等3种应用广泛的低影响开发措施,归纳了此类措施长期运行情况下可能出现的雨水径流入渗、雨水资源利用、设施功能衰减等方面的风险,并提出低影响开发措施的升级改造、雨水资源利用标准的制定、管理运维方案的完善、国家政策支持与社会各界参与等风险防控对策。通过对海绵城市低影响开发措施应用的风险研究,提出未来海绵城市建设的研究重点应放在设施机理研究、寿命计算与效益评价、智慧化建设等方面。

管材拉弯工艺及数值模拟分析

拉弯是管材弯曲成形的重要工艺方法,采用有限元分析软件ANSYS/LS-DYNA对不同工艺参数下的管材拉弯成形过程进行了数值模拟,通过改变相对弯曲半径R/D和相对弯曲厚度t/D,分析了拉弯工艺参数对成形过程的影响。研究结果表明:通过增大相对弯曲半径R/D或增大相对弯曲厚度t/D,降低弯曲件的等效应力,可以有效控制弯曲件壁厚的变化,有助于提高管材拉弯成形的质量。

基础设施建设与文旅产业的耦合研究

目前我国基础设施建设存在投融资机制单一、运营管理机制不完善的问题,而文旅项目的引入是解决此问题的有效途径。归纳公共基础设施中融入文旅项目存在的市场活力不足、资源利用率低、投融资力度薄弱等三大难点,通过典型案例分析,总结出标志点位文旅策划、本土文化依托、轻资产活动策划等解决方案。

A low specific on-resistance SOI LDMOS with a novel junction field plate

A low specific on-resistance SO1 LDMOS with a novel junction field plate （JFP） is proposed and investigated theo- retically. The most significant feature of the JFP LDMOS is a PP-N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buffed oxide layer （BOX） and thus widens the vertical conduction area. As a result, the breakdown voltage （BV） is improved and the specific on-resistance （Ron,sp） is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ.cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.

WePark停车

本WePark智能停车系统的布置,相对有下列的优点,其中(1)使用智能地锁实现场地的布置,可以实现停车场的分布式控制和集中式的统筹管理;(2)使用更加高效和稳定的车位定位系统,在大范围的导航中,本系统在客户端上使用百度地图进行导航,当到达指定的停车场附近时,在室内停车场路口设置一个通过zigbee无线控制的液晶导航屏幕,以及加上指定车位处的指引灯设计,使得室内导航系统更加可靠稳定;(3)实现多平台支持,保证数据联通,本系统支持微信、安卓、IOS三大平台,三大平台共用数据库,数据联通迅速,满足不同人群的需要;(4)信息传送为无线形式,利用地锁使场地改造成本低,只要将智能地锁安装在车位上,开机配置后即可使用,地锁用干电池供电,可长期工作,无需另外布线,大大减少了改造车位的成本。

Ultra-low specific on-resistance vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench（HK TG VDMOS） is proposed in this paper.The HK TG VDMOS features a high-k（HK） trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage（BV）.Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction（SJ） vertical double-diffused metal-oxide semiconductor（VDMOS）,the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS（TG VDMOS） and conventional superjunction trench gate VDMOS（SJ TG CDMOS）.

Ultralow Specific on-Resistance Trench MOSFET with a U-Shaped Extended Gate

An ultralow specific on-resistance （Ron,sp） trench metal-oxide-semiconductor field effect transistor （MOSFET） with an improved off-state breakdown voltage （BV） is proposed. It features a U-shaped gate around the drift region and an oxide trench inserted in the drift region （UG MOSFET）. In the on-state, the U-shaped gate induces a high density electron accumulation layer along its sidewall, which provides a low-resistance current path from the source to the drain, realizing an ultralow Ron,sp. The value of Ron,sp is almost independent of the drift doping concentration, and thus the UG MOSFET breaks through the contradiction relationship between R p and the off-state BV. Moreover, the oxide trench folds the drift region, enabling the UG MOSFET to support a high BV with a shortened cell pitch. The UG MOSFET achieves an Ron,sp of 2 mΩ·cm^2 and an improved BV of 216 V, superior to the best existing state-of-the-art transistors at the same BV level

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

A low specific on-resistance（Ron,sp） integrable silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is proposed and investigated by simulation.The MOSFET features a recessed drain as well as dual gates,which consist of a planar gate and a trench gate extended to the buried oxide layer（BOX）（DGRD MOSFET）.First,the dual gates form dual conduction channels,and the extended trench gate also acts as a field plate to improve the electric field distribution.Second,the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path.Third,the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions.All of these sharply reduce Ron,sp and maintain a high breakdown voltage（BV）.The BV of 233 V and Ron,sp of 4.151 mΩ·cm2（VGS = 15 V） are obtained for the DGRD MOSFET with 15-μm half-cell pitch.Compared with the trench gate SOI MOSFET and the conventional MOSFET,Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV,respectively.The trench gate extended to the BOX synchronously acts as a dielectric isolation trench,simplifying the fabrication processes.

A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

A novel low specific on-resistance （Ron,sp） silicon-on-insulator （SO1） p-channel lateral double-diffused metal-oxide semiconductor （pLDMOS） compatible with high voltage （HV） n-channel LDMOS （nLDMOS） is proposed. The pLDMOS is built in the N-type SO1 layer with a buried P-type layer acting as a current conduction path in the on-state （BP SOl pLD- MOS）. Its superior compatibility with the HV nLDMOS and low voltage （LV） complementary metal-oxide semiconductor （CMOS） circuitry which are formed on the N-SOl layer can be obtained. In the off-state the P-buried layer built in the NSOI layer causes multiple depletion and electric field reshaping, leading to an enhanced （reduced） surface field （RESURF） effect. The proposed BP SO1 pLDMOS achieves not only an improved breakdown voltage （BV） but also a significantly reduced Ron,sp. The BV of the BP SO1 pLDMOS increases to 319 V from 215 V of the conventional SO1 pLDMOS at the same half cell pitch of 25 μm, and Ron,sp decreases from 157 mΩ.cm2 to 55 mΩ.cm2. Compared with the PW SO1 pLDMOS, the BP SO1 pLDMOS also reduces the Ron,sp by 34% with almost the same BV.

A High Figure-of-Merit SOI MOSFET with a Double-Sided Charge Oxide-Trench

A novel silicon-on-insulator(SOI)metal-oxide-semiconductor field effect transistor(MOSFET)with a high figure of merit(FOM)is proposed.The device features a double-sided charge oxide-trench(DCT)and a trench gate extended to the buried oxide.First,the oxide trench causes multiple-dimensional depletion in the drift region,which not only improves the electric field(E-field)strength,but also enhances the reduced surface field effect.Second,self-adaptive charges are collected in the DCT,which enhances the E-field strength of the trench oxide.Third,the oxide trench folds the drift region along the vertical direction,reducing the device cell pitch.Fourth,one side of the DCT regions acts as the body contact of p-well to reduce cell pitch and specific on-resistance(R_(on,sp))further.Compared with a trench gate lateral double-diffused MOSFET,the DCT MOSFET increases the breakdown voltage(BV)from 53 V to 158 V at the same cell pitch of 3.5μm,or reduces the cell pitch by 60%and Ron,sp by 70%at the same BV.The FOM(FOM=BV^(2)/Ron,sp)of the proposed structure is 23 MW/cm^(2).

高k介质电导增强SOI LDMOS机理与优化设计

本文提出一种高k介质电导增强SOI LDMOS新结构(HK CE SOI LDMOS),并研究其机理.HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻.借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系.结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%—18%,同时比导通电阻降低13%—20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题.

Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

An improved breakdown voltage （BV） SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches （DTMOS）, an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide （BOX）. The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide （eox） than that of Si （esi）. Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF （reduced surface field） effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit （HVIC）, effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.

Ultralow specific on-resistance high voltage trench SOI LDMOS with enhanced RESURF effect

A RESURF-enhanced high voltage SOl LDMOS （ER-LDMOS） with an ultralow specific on-resistance （Ron, sp） is proposed. The device features an oxide trench in the drift region, a P-pillar at the sidewall of the trench, and a buried P-layer （BPL） under the trench. First, the P-pillar adjacent to the P-body not only acts as a vertical junction termination extension （JTE）, but also forms a vertical reduced surface field （RESURF） structure with the N- drift region. Both of them optimize the bulk electric field distributions and increase the doping concentration of the drift region. Second, the BPL together with the N-drift region and the buried oxide layer （BOX） exhibits a triple- RESURF effect, which further improves the bulk field distributions and the doping concentration. Additionally, multiple-directional depletion is induced owing to the P-pillar, the BPL, and two MIS-like structures consisting of the N-drift region combined with the oxide trench and the BOX. As a result, a significantly enhanced-RESURF effect is achieved, leading to a high breakdown voltage （BV） and a low Ron, sp. Moreover, the oxide trench folds the drift region in the vertical direction, resulting in a reduced cell pitch and thus Ron, sp. Simulated results show that the ER-LDMOS improves BV by 67% and reduces Ron, sp by 91% compared with the conventional trench LDMOS at the same cell pitch.

An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

A low specific on-resistance（R on;sp/ SOI NBL TLDMOS（silicon-on-insulator trench LDMOS with an N buried layer） is proposed. It has three features： a thin N buried layer（NBL） on the interface of the SOI layer/buried oxide（BOX） layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer.First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the R on;sp. Second, in the y-direction, the BOX＇s electric field（E-field） strength is increased to 154 V/ m from48 V/ m of the SOI Trench Gate LDMOS（SOI TG LDMOS） owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage（BV）, but also reduces the cell pitch and R on;sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 m, and decreases the R on;sp by 80% at the same BV.