A direct conversion receiver with optimized tolerance to local carrier interference is designed and implemented in a 0.18μm 1P6M mixed-signal CMOS process for a 900MHz RFID reader transceiver. A baseband amplifier wi...A direct conversion receiver with optimized tolerance to local carrier interference is designed and implemented in a 0.18μm 1P6M mixed-signal CMOS process for a 900MHz RFID reader transceiver. A baseband amplifier with series feedback topology is proposed to achieve passive mixer buffering,baseband DC cancellation,and signal amplification simultaneously. The receiver has a measured input ldB compression point of - 4dBm and a sensitivity of - 70dBm when 10dB SNR for digital demodulation is required. The receiver is integrated in a reader transceiver chip and consumes 90mA from a 1.8V supply.展开更多
A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional G...A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional Gilbert mixer pair in commutating mode. A quadrature down-conversion mixer based on this topology is designed and optimized for an ultra high frequency RFID reader. Operating in the 915MHz ISM band, the presented quadrature mixer measures a conversion gain of 12.5dB,an IIP3 of 10dBm, an IIP2 of 58dBm, and an SSB noise figure of 17.6riB. The chip was fabricated in a 0. 18μm 1P6M RF CMOS process and consumes only 3mA of current from a 1.8V power supply.展开更多
An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit...An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.展开更多
基金the Science and Technology Commission of Shanghai Municipality(No.057062010)the EU BRIDGE Project(No.033546)~~
文摘A direct conversion receiver with optimized tolerance to local carrier interference is designed and implemented in a 0.18μm 1P6M mixed-signal CMOS process for a 900MHz RFID reader transceiver. A baseband amplifier with series feedback topology is proposed to achieve passive mixer buffering,baseband DC cancellation,and signal amplification simultaneously. The receiver has a measured input ldB compression point of - 4dBm and a sensitivity of - 70dBm when 10dB SNR for digital demodulation is required. The receiver is integrated in a reader transceiver chip and consumes 90mA from a 1.8V supply.
文摘A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional Gilbert mixer pair in commutating mode. A quadrature down-conversion mixer based on this topology is designed and optimized for an ultra high frequency RFID reader. Operating in the 915MHz ISM band, the presented quadrature mixer measures a conversion gain of 12.5dB,an IIP3 of 10dBm, an IIP2 of 58dBm, and an SSB noise figure of 17.6riB. The chip was fabricated in a 0. 18μm 1P6M RF CMOS process and consumes only 3mA of current from a 1.8V power supply.
文摘An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.
