Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed wit...Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.展开更多
An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit...An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.展开更多
大规模相控阵是解决毫米波无线传输距离受限的核心关键技术.传统的毫米波相控阵通常基于化合物半导体芯片加以实现,该类芯片成本高昂且难以实现系统单片集成,极大地限制了传统相控阵的应用范围.本文报道了基于CMOS成熟工艺的毫米波芯片...大规模相控阵是解决毫米波无线传输距离受限的核心关键技术.传统的毫米波相控阵通常基于化合物半导体芯片加以实现,该类芯片成本高昂且难以实现系统单片集成,极大地限制了传统相控阵的应用范围.本文报道了基于CMOS成熟工艺的毫米波芯片设计及收发通道数为4096(4096发射/4096接收)的超大规模集成相控阵实现技术.CMOS体硅工艺具有集成度高、成本低廉等优势,但面临有源器件高频性能差、无源器件及互连线高频损耗大、高低温性能差异大等一系列技术瓶颈.通过引入电流复用跨导增强型低噪声放大器、基于新型版图结构的高效率功率放大器、矢量调制型数控无源移相器、基于电容补偿的超宽带衰减器、紧凑型功分器,以及高低温自适应偏置电路等技术,可以较好地解决CMOS体硅工艺所面临的上述瓶颈问题.基于65 nm CMOS体硅工艺,所实现的Ka频段CMOS相控阵芯片噪声系数为3.0 d B,发射通道效率为15%,无需校准即可实现精确幅相控制,相关测试结果表明所研制的低成本相控阵芯片具有集成度高、幅相控制精确等优势,噪声系数等关键技术指标接近砷化镓工艺.以此为基础,本文给出了基于多层混压PCB工艺的1024发射/1024接收超大规模"集成相控阵"设计技术,并将其扩展至4096发射/4096接收相控阵规模,最后给出了低成本、高集成宽带卫星移动通信终端在车载和船载条件下的示范应用结果.展开更多
文摘Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.
文摘An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.
文摘大规模相控阵是解决毫米波无线传输距离受限的核心关键技术.传统的毫米波相控阵通常基于化合物半导体芯片加以实现,该类芯片成本高昂且难以实现系统单片集成,极大地限制了传统相控阵的应用范围.本文报道了基于CMOS成熟工艺的毫米波芯片设计及收发通道数为4096(4096发射/4096接收)的超大规模集成相控阵实现技术.CMOS体硅工艺具有集成度高、成本低廉等优势,但面临有源器件高频性能差、无源器件及互连线高频损耗大、高低温性能差异大等一系列技术瓶颈.通过引入电流复用跨导增强型低噪声放大器、基于新型版图结构的高效率功率放大器、矢量调制型数控无源移相器、基于电容补偿的超宽带衰减器、紧凑型功分器,以及高低温自适应偏置电路等技术,可以较好地解决CMOS体硅工艺所面临的上述瓶颈问题.基于65 nm CMOS体硅工艺,所实现的Ka频段CMOS相控阵芯片噪声系数为3.0 d B,发射通道效率为15%,无需校准即可实现精确幅相控制,相关测试结果表明所研制的低成本相控阵芯片具有集成度高、幅相控制精确等优势,噪声系数等关键技术指标接近砷化镓工艺.以此为基础,本文给出了基于多层混压PCB工艺的1024发射/1024接收超大规模"集成相控阵"设计技术,并将其扩展至4096发射/4096接收相控阵规模,最后给出了低成本、高集成宽带卫星移动通信终端在车载和船载条件下的示范应用结果.
