A two-stage monolithic microwave integrated circuit （MMIC） low noise amplifier （LNA） fabricated in 0.5 μm GaAs pHEMT is presented. The Miller effect introduced by the parasitic gate-drain capacitance is utilized ...A two-stage monolithic microwave integrated circuit （MMIC） low noise amplifier （LNA） fabricated in 0.5 μm GaAs pHEMT is presented. The Miller effect introduced by the parasitic gate-drain capacitance is utilized to decrease the value of the input inductor. Additionally, the input on-chip inductor is a novel high Q gradual structure. The noise figure is reduced with these two methods. With good input and output matching, the LNA achieves a noise figure of 0.75 dB and a small signal gain of 32.7 dB over 698-806 MHz. The input 1 dB compression point is -21.8 dBm and the input third order interception point is -10 dBm.展开更多
This paper presents a 60 GHz balanced low noise amplifier. Compared with single-ended structures, the balanced structure can obtain a better input/output return loss, a lower noise figure （NF）, a 3 dB improvement of...This paper presents a 60 GHz balanced low noise amplifier. Compared with single-ended structures, the balanced structure can obtain a better input/output return loss, a lower noise figure （NF）, a 3 dB improvement of the 1 dB compression point, a 6 dB improvement of 1M3 and a doubled dynamic range. Each single-ended amplifier in this paper uses a four-stage cascade structure to achieve a high gain in broadband. At the operating frequency range of 59-64 GHz, the small signal gain of the balanced amplifier is more than 20 dB. Both the input and output return losses are less than -12 dB. The output 1 dB compression power is 10.5 dBm at 60 GHz. The simulation result for the NF is better than 3.9 dB. The chip is fabricated using a 0.15 μm GaAs pHEMT process with a size of 2.25 × 1.7 mm2.展开更多
基金Project supported by the External Cooperation Program of BIC,Chinese Academy of Sciences(No.172511KYSB20130108)
文摘A two-stage monolithic microwave integrated circuit （MMIC） low noise amplifier （LNA） fabricated in 0.5 μm GaAs pHEMT is presented. The Miller effect introduced by the parasitic gate-drain capacitance is utilized to decrease the value of the input inductor. Additionally, the input on-chip inductor is a novel high Q gradual structure. The noise figure is reduced with these two methods. With good input and output matching, the LNA achieves a noise figure of 0.75 dB and a small signal gain of 32.7 dB over 698-806 MHz. The input 1 dB compression point is -21.8 dBm and the input third order interception point is -10 dBm.
基金supported by the External Cooperation Program of BIC,Chinese Academy of Sciences(No.172511KYSB20130108)
文摘This paper presents a 60 GHz balanced low noise amplifier. Compared with single-ended structures, the balanced structure can obtain a better input/output return loss, a lower noise figure （NF）, a 3 dB improvement of the 1 dB compression point, a 6 dB improvement of 1M3 and a doubled dynamic range. Each single-ended amplifier in this paper uses a four-stage cascade structure to achieve a high gain in broadband. At the operating frequency range of 59-64 GHz, the small signal gain of the balanced amplifier is more than 20 dB. Both the input and output return losses are less than -12 dB. The output 1 dB compression power is 10.5 dBm at 60 GHz. The simulation result for the NF is better than 3.9 dB. The chip is fabricated using a 0.15 μm GaAs pHEMT process with a size of 2.25 × 1.7 mm2.
