As the thickness of an SOI layer varies,a minimum breakdown voltage is reached when the thickness is about 2μm. The vertical electric field of the SOI LDMOS with a drift region which is vertically linearly graded is ...As the thickness of an SOI layer varies,a minimum breakdown voltage is reached when the thickness is about 2μm. The vertical electric field of the SOI LDMOS with a drift region which is vertically linearly graded is constant. The vertically linearly graded concentration drift can be achieved by impurity implanting followed by thermal diffusion. In this way,the vertical breakdown voltage of SOI LDMOS with 2μm thickness SOI layer can be improved by 43%. The on-state resistance is lowered by 24 % because of the higher impurity concentration of the SOI surface.展开更多
集成电路制造技术的迅速发展已经可以把一个完整的电子系统集成到一个芯片上即所谓的系统级芯片 (Sys tem on Chip ,简称SoC)。传统的设计方法是将硬件和软件分开来设计的 ,在硬件设计完成并生产出样片后才能调试软件。本文介绍了针对...集成电路制造技术的迅速发展已经可以把一个完整的电子系统集成到一个芯片上即所谓的系统级芯片 (Sys tem on Chip ,简称SoC)。传统的设计方法是将硬件和软件分开来设计的 ,在硬件设计完成并生产出样片后才能调试软件。本文介绍了针对于系统级芯片设计的软硬件协同设计技术 (co design)的概念和设计流程 。展开更多
文摘As the thickness of an SOI layer varies,a minimum breakdown voltage is reached when the thickness is about 2μm. The vertical electric field of the SOI LDMOS with a drift region which is vertically linearly graded is constant. The vertically linearly graded concentration drift can be achieved by impurity implanting followed by thermal diffusion. In this way,the vertical breakdown voltage of SOI LDMOS with 2μm thickness SOI layer can be improved by 43%. The on-state resistance is lowered by 24 % because of the higher impurity concentration of the SOI surface.
文摘集成电路制造技术的迅速发展已经可以把一个完整的电子系统集成到一个芯片上即所谓的系统级芯片 (Sys tem on Chip ,简称SoC)。传统的设计方法是将硬件和软件分开来设计的 ,在硬件设计完成并生产出样片后才能调试软件。本文介绍了针对于系统级芯片设计的软硬件协同设计技术 (co design)的概念和设计流程 。
