Enhanced Wideband Frequency Estimation via FFT: Leveraging Polynomial Interpolation and Array Indexing

Accurate frequency estimation in a wideband digital receiver using the FFT algorithm encounters challenges, such as spectral leakage resulting from the FFT’s assumption of signal periodicity. High-resolution FFTs pose computational demands, and estimating non-integer multiples of frequency resolution proves exceptionally challenging. This paper introduces two novel methods for enhanced frequency precision: polynomial interpolation and array indexing, comparing their results with super-resolution and scalloping loss. Simulation results demonstrate the effectiveness of the proposed methods in contemporary radar systems, with array indexing providing the best frequency estimation despite utilizing maximum hardware resources. The paper demonstrates a trade-off between accurate frequency estimation and hardware resources when comparing polynomial interpolation and array indexing.

High Sensitivity Digital Instantaneous Frequency Measurement Receiver for Precise Frequency Analysis

There are numerous applications, such as Radar, that leverage wideband technology. However, the presence of noise introduces certain limitations and challenges. It is crucial to harness wideband technology for applications demanding the rapid and precise transmission of diverse information from one point to another within a short timeframe. The ability to report a signal without tuning within the input bandwidth stands out as one of the advantages of employing a digital wideband receiver. As indicated, a digital wideband receiver plays a pivotal role in achieving high precision and accuracy. The primary distinction between Analog and Digital Instantaneous Frequency Measurement lies in the fact that analog Instantaneous Frequency Measurement (IFM) receivers have traditionally covered extensive input bandwidths, reporting one accurate frequency per short pulse. In the contemporary landscape, digital IFM systems utilize high-sampling-rate Analog-to-Digital Converters (ADC) along with Hilbert transforms to generate two output channels featuring a 90-degree phase shift. This paper explores the improvement of sensitivity in current digital IFM receivers. The optimization efforts target the Hilbert transform and autocorrelations architectures, aiming to refine the system’s ability to report fine frequencies within a noisy wide bandwidth environment, thereby elevating its overall sensitivity.

A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, i.e., configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm2 and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.