System-on-Chip Design Using High-Level Synthesis Tools

This paper addresses the challenges of System-on-Chip designs using High-Level Synthesis (HLS). HLS tools convert algorithms designed in C into hardware modules. This approach is a practical choice for developing complex applications. Nevertheless, certain hardware considerations are required when writing C applications for HLS tools. Hence, in order to demonstrate the fundamental hardware design concepts, a case studyis presented. Fast Fourier Transform (FFT) implementation in ANSI C is examined in order to explore the important design issues such as concurrency, data recurrences and memory accesses that need to be resolved before generating the hardware using HLS tools. There are additional language constraints that need to be addressed including use of pointers, recursion and floating point types.

Polymorphic Computing: Definition, Trends, and a New Agent-Based Architecture

Polymorphic computing is widely seen as next evolutionary step in designing advanced computing architectures. This paper presents a brief history of reconfigurable and polymorphic computing, and highlights the recent trends and challenges. A novel polymorphic architecture featuring programmable memory event triggers and a new concept of control agents is proposed. This architecture can provide dynamic load balancing, distributed control, separated memory and processing fabrics, configurable memory blocks, and task-optimized computation.

Human Friendly Interface Design for Virtual Fitting Room Applications on Android Based Mobile Devices

This paper presents an image processing design flow for virtual fitting room (VFR) applications, targeting both personal computers and mobile devices. The proposed human friendly interface is implemented by a three-stage algorithm: Detection and sizing of the user's body, detection of reference points based on face detection and augmented reality markers, and superimposition of the clothing over the user's image. Compared to other existing VFR systems, key difference is the lack of any proprietary hardware components or peripherals. Proposed VFR is software based and designed to be universally compatible as long as the device has a camera. Furthermore, JAVA implementation on Android based mobile systems is computationally efficient and it can run in real-time on existing mobile devices.

FPGA-Based Traffic Sign Recognition for Advanced Driver Assistance Systems

This paper presents the implementation of an embedded automotive system that detects and recognizes traffic signs within a video stream. In addition, it discusses the recent advances in driver assistance technologies and highlights the safety motivations for smart in-car embedded systems. An algorithm is presented that processes RGB image data, extracts relevant pixels, filters the image, labels prospective traffic signs and evaluates them against template traffic sign images. A reconfigurable hardware system is described which uses the Virtex-5 Xilinx FPGA and hardware/software co-design tools in order to create an embedded processor and the necessary hardware IP peripherals. The implementation is shown to have robust performance results, both in terms of timing and accuracy.

Direction of Arrival Estimation and Localization Using Acoustic Sensor Arrays

Sound source localization has numerous applications such as detection and localization of mechanical or structural failures in vehicles and buildings or bridges, security systems, collision avoidance, and robotic vision. The paper presents the design of an anechoic chamber, sensor arrays and an analysis of how the data acquired from the sensors could be used for sound source localization and object detection. An anechoic chamber is designed to create a clean environment which isolates the experiment from external noises and reverberation echoes. An FPGA based data acquisition system is developed for a flexible acoustic sensor array platform. Using this sensor platform, we investigate direction of arrival estimation and source localization experiments with different geometries and with different numbers of sensors. We further present a discussion of parameters that influence the sensitivity and accuracy of the results of these experiments.

Chirplet Signal and Empirical Mode Decompositions of Ultrasonic Signals for Echo Detection and Estimation

In this study, the performance of chirplet signal decomposition (CSD) and empirical mode decomposition (EMD) coupled with Hilbert spectrum have been evaluated and compared for ultrasonic imaging applications. Numerical and experimental results indicate that both the EMD and CSD are able to decompose sparsely distributed chirplets from noise. In case of signals consisting of multiple interfering chirplets, the CSD algorithm, based on successive search for estimating optimal chirplet parameters, outperforms the EMD algorithm which estimates a series of intrinsic mode functions (IMFs). In particular, we have utilized the EMD as a signal conditioning method for Hilbert time-frequency representation in order to estimate the arrival time and center frequency of chirplets in order to quantify the ultrasonic signals. Experimental results clearly exhibit that the combined EMD and CSD is an effective processing tools to analyze ultrasonic signals for target detection and pattern recognition.

A Design Flow for Robust License Plate Localization and Recognition in Complex Scenes

In this paper, we present a new design flow for robust license plate localization and recognition. The algorithm consists of three stages: 1) license plate localization;2) character segmentation;and 3) feature extraction and character recognition. The algorithm uses Mexican hat operator for edge detection and Euler number of a binary image for identifying the license plate region. A pre-processing step using median filter and contrast enhancement is employed to improve the character segmentation performance in case of low resolution and blur images. A unique feature vector comprised of region properties, projection data and reflection symmetry coefficient has been proposed. Back propagation artificial neural network classifier has been used to train and test the neural network based on the extracted feature. A thorough testing of algorithm is performed on a database with varying test cases in terms of illumination and different plate conditions. Practical considerations like existence of another text block in an image, presence of dirt or shadow on or near license plate region, license plate with rows of characters and sensitivity to license plate dimensions have been addressed. The results are encouraging with success rate of 98.10% for license plate localization and 97.05% for character recognition.

Security Policy Management Process within Six Sigma Framework

This paper presents a management process for creating adaptive, real-time security policies within the Six Sigma (6σ) framework. A key challenge for the creation of a management process is the integration with models of known Industrial processes. One of the most used industrial process models is Six Sigma which is a business management model wherein customer centric needs are put in perspective with business data to create an efficient system. The security policy creation and management process proposed in this paper is based on the Six Sigma model and presents a method to adapt security goals and risk management of a computing service. By formalizing a security policy management process within an industrial process model, the adaptability of this model to existing industrial tools is seamless and offers a clear risk based policy decision framework. In particular, this paper presents the necessary tools and procedures to map Six Sigma DMAIC (Define-Measure-Analyze-Improve-Control) methodology to security policy management.

Fast Signed-Digit Multi-operand Decimal Adders

Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.

A Reconfigurable Network-on-Chip Datapath for Application Specific Computing

This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functional elements can be dynamically allocated for application specific optimizations, enabling polymorphic computing. Using a modified network simulator, performance of several NoC topologies and parameters are investigated with standard benchmark programs, including fine grain and coarse grain computations. Simulation results highlight the flexibility and scalability of the proposed polymorphic NoC processor for a wide range of application domains.