Electric field dependence of spin qubit in a Si-MOS quantum dot

Valley, the intrinsic feature of silicon, is an inescapable subject in silicon-based quantum computing. At the spin–valley hotspot, both Rabi frequency and state relaxation rate are significantly enhanced. With protection against charge noise, the valley degree of freedom is also conceived to encode a qubit to realize noise-resistant quantum computing.Here, based on the spin qubit composed of one or three electrons, we characterize the intrinsic properties of valley in an isotopically enriched silicon quantum dot(QD) device. For one-electron qubit, we measure two electric-dipole spin resonance(EDSR) signals which are attributed to partial occupation of two valley states. The resonance frequencies of two EDSR signals have opposite electric field dependences. Moreover, we characterize the electric field dependence of the upper valley state based on three-electron qubit experiments. The difference of electric field dependences of the two valleys is 52.02 MHz/V, which is beneficial for tuning qubit frequency to meet different experimental requirements. As an extension of electrical control spin qubits, the opposite electric field dependence is crucial for qubit addressability,individual single-qubit control and two-qubit gate approaches in scalable quantum computing.

Threshold-independent method for single-shot readout of spin qubits in semiconductor quantum dots

The single-shot readout data process is essential for the realization of high-fidelity qubits and fault-tolerant quantum algorithms in semiconductor quantum dots. However, the fidelity and visibility of the readout process are sensitive to the choice of the thresholds and limited by the experimental hardware. By demonstrating the linear dependence between the measured spin state probabilities and readout visibilities along with dark counts, we describe an alternative threshold-independent method for the single-shot readout of spin qubits in semiconductor quantum dots. We can obtain the extrapolated spin state probabilities of the prepared probabilities of the excited spin state through the threshold-independent method. We then analyze the corresponding errors of the method, finding that errors of the extrapolated probabilities cannot be neglected with no constraints on the readout time and threshold voltage. Therefore, by limiting the readout time and threshold voltage, we ensure the accuracy of the extrapolated probability. We then prove that the efficiency and robustness of this method are 60 times larger than those of the most commonly used method. Moreover, we discuss the influence of the electron temperature on the effective area with a fixed external magnetic field and provide a preliminary demonstration for a single-shot readout of up to 0.7K/1.5T in the future.

Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-κ Dielectrics and SiGe Epitaxial Substrates

A novel high-κ~ A1203/HfO2/AI203 nanolaminate charge trapping memory capacitor structure based on SiGe substrates with low interface densities is successfully fabricated and investigated. The memory capacitor exhibits excellent program-erasable characteristics. A large memory window of ~4 V, a small leakage current density of ~2 ×10-6 Acre-2 at a gate voltage of 7V, a high charge trapping density of 1.42 × 1013 cm-2 at a working vo]tage of 4-10 V and good retention characteristics are observed. Furthermore, the programming （△ VFB = 2.8 V at 10 V for 10μs） and erasing speeds （△VFB =-1.7 V at -10 V for 10μs） of the fabricated capacitor based on SiGe substrates are significantly improved as compared with counterparts reported earlier. It is concluded that the high-κ Al2O3/HfO2/Al2O3 nanolaminate charge trapping capacitor structure based on SiGe substrates is a promising candidate for future nano-scaled nonvolatile flash memory applications.

Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel

We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at ＋11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s＇ retention. In addition, the leakage current density is lower than 2.52 × 10^（-7） A·cm^（-2） below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.