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Dependence of short channel length on negative/positive bias temperature instability (NBTI/PBTI) for 3D FinFET devices
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作者 Ren-Ren Xu Qing-Zhu Zhang +4 位作者 Long-Da Zhou Hong Yang Tian-Yang Gai hua-xiang yin Wen-Wu Wang 《Chinese Physics B》 SCIE EI CAS CSCD 2022年第1期529-534,共6页
A comprehensive study of the negative and positive bias temperature instability(NBTI/PBTI)of 3D FinFET devices with different small channel lengths is presented.It is found while with the channel lengths shrinking fro... A comprehensive study of the negative and positive bias temperature instability(NBTI/PBTI)of 3D FinFET devices with different small channel lengths is presented.It is found while with the channel lengths shrinking from 100 nm to 30 nm,both the NBTI characteristics of p-FinFET and PBTI characteristics of n-FinFET turn better.Moreover,the channel length dependence on NBTI is more serious than that on PBTI.Through the analysis of the physical mechanism of BTI and the simulation of 3-D stress in the FinFET device,a physical mechanism of the channel length dependence on NBTI/PBTI is proposed.Both extra fluorine passivation in the corner of bulk oxide and stronger channel stress in p-FinFETs with shorter channel length causes less NBTI issue,while the extra nitrogen passivation in the corner of bulk oxide induces less PBTI degradation as the channel length decreasing for n-FinFETs.The mechanism well matches the experimental result and provides one helpful guide for the improvement of reliability issues in the advanced FinFET process. 展开更多
关键词 bias temperature instability(BTI) channel length stress FINFET
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Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-κ Dielectrics and SiGe Epitaxial Substrates
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作者 Zhao-Zhao Hou Gui-Lei Wang +4 位作者 Jin-Juan Xiang Jia-Xin Yao Zhen-Hua Wu Qing-Zhu Zhang hua-xiang yin 《Chinese Physics Letters》 SCIE CAS CSCD 2017年第9期95-99,共5页
A novel high-κ~ A1203/HfO2/AI203 nanolaminate charge trapping memory capacitor structure based on SiGe substrates with low interface densities is successfully fabricated and investigated. The memory capacitor exhibit... A novel high-κ~ A1203/HfO2/AI203 nanolaminate charge trapping memory capacitor structure based on SiGe substrates with low interface densities is successfully fabricated and investigated. The memory capacitor exhibits excellent program-erasable characteristics. A large memory window of ~4 V, a small leakage current density of ~2 ×10-6 Acre-2 at a gate voltage of 7V, a high charge trapping density of 1.42 × 1013 cm-2 at a working vo]tage of 4-10 V and good retention characteristics are observed. Furthermore, the programming (△ VFB = 2.8 V at 10 V for 10μs) and erasing speeds (△VFB =-1.7 V at -10 V for 10μs) of the fabricated capacitor based on SiGe substrates are significantly improved as compared with counterparts reported earlier. It is concluded that the high-κ Al2O3/HfO2/Al2O3 nanolaminate charge trapping capacitor structure based on SiGe substrates is a promising candidate for future nano-scaled nonvolatile flash memory applications. 展开更多
关键词 Dielectrics and SiGe Epitaxial Substrates Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High
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Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel
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作者 Zhao-Zhao Hou Gui-Lei Wang +2 位作者 Jia-Xin Yao Qing-Zhu Zhang hua-xiang yin 《Chinese Physics Letters》 SCIE CAS CSCD 2018年第5期110-114,共5页
We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure(named as MONOS), utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent pr... We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure(named as MONOS), utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at +11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s' retention. In addition, the leakage current density is lower than 2.52 × 10^(-7) A·cm^(-2) below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics. 展开更多
关键词 FB Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel
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Performance improvements in complementary metal oxide semiconductor devices and circuits based on fin field-effect transistors using 3-nm ferroelectric Hf_(0.5)Zr_(0.5)O_(2)
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作者 Zhao-Hao Zhang Yan-Na Luo +8 位作者 Gao-Bo Xu Jia-Xin Yao Zhen-Hua Wu Hong-Bin Zhao Qing-Zhu Zhang hua-xiang yin Jun Luo Wen-Wu Wang Hai-Ling Tu 《Rare Metals》 SCIE EI CAS CSCD 2024年第7期3242-3249,共8页
In this work,a conventional HfO_(2) gate dielectric layer is replaced with a 3-nm ferroelectric(Fe) HZO layer in the gate stacks of advanced fin field-effect transistors(FinFETs).Fe-induced characteristics,e.g.,negati... In this work,a conventional HfO_(2) gate dielectric layer is replaced with a 3-nm ferroelectric(Fe) HZO layer in the gate stacks of advanced fin field-effect transistors(FinFETs).Fe-induced characteristics,e.g.,negative drain induced barrier lowering(N-DIBL) and negative differential resistance(NDR),are clearly observed for both p-and n-type HZO-based FinFETs.These characteristics are attributed to the enhanced ferroelectricity of the 3-nm hafnium zirconium oxide(HZO) film,caused by Al doping from the TiAlC capping layer.This mechanism is verified for capacitors with structures similar to the FinFETs.Owing to the enhanced ferroelectricity and N-DIBL phenomenon,the drain current(I_(DS))of the HZO-FinFETs is greater than that of HfO_(2)-FinFETs and obtained at a lower operating voltage.Accordingly,circuits based on HZO-FinFET achieve higher performance than those based on HfO_(2)-FinFET at a low voltage drain(V_(DD)),which indicates the application feasibility of the HZO-FinFETs in the ultralow power integrated circuits. 展开更多
关键词 FINFET FERROELECTRIC Hafnium zirconium oxide Subthreshold swing Low power
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