A 128×128 SPAD LiDAR sensor with column-parallel 25 ps resolution TA-ADCs

This paper presents a design of single photon avalanche diode(SPAD)light detection and ranging(LiDAR)sensor with 128×128 pixels and 128 column-parallel time-to-analog-merged-analog-to-digital converts(TA-ADCs).Unlike the conventional TAC-based SPAD LiDAR sensor,in which the TAC and ADC are separately implemented,we propose to merge the TAC and ADC by sharing their capacitors,thus avoiding the analog readout noise of TAC’s output buffer,improving the conversion rate,and reducing chip area.The reverse start-stop logic is employed to reduce the power of the TA-ADC.Fabricated in a 180 nm CMOS process,our prototype sensor exhibits a timing resolution of 25 ps,a DNL of+0.30/−0.77 LSB,an INL of+1.41/−2.20 LSB,and a total power consumption of 190 mW.A flash LiDAR system based on this sensor demonstrates the function of 2D/3D imaging with 128×128 resolution,25 kHz inter-frame rate,and sub-centimeter ranging precision.

Preface to Special Topic on Integrated Circuits, Technologies and Applications

This Special Topic of the Journal of Semiconductors(JoS)features expanded versions of key articles presented at the 2023 IEEE International Conference on Integrated Circuits Technologies and Applications(ICTA),which was held in Hefei,Anhui,China,from October 27 to 29,2023.IEEE ICTA is an IEEE flagship conference in the field of integrated circuits(IC)in China,which provides a communication platform for sharing the state-of-the-art techniques from experts in the field of ICs.Among the 93 papers presented at ICTA 2023,the Technical Program Committee and the Award Committee have selected 4 high-quality articles to recommend to the Special Topic of JoS,covering a wide range of technical fields,including one paper on RF ICs,two papers on Analog ICs and one paper on Wireline ICs.

Subthreshold analog techniques

IEEE J.Solid-State Circuits,2019,doi:10.1109/JSSC.2018.2889847Low power is a fundamental requirement in state-ofthe-art IC designs,where lower and scalable supply voltagesare demanded due to the power benefits of digital circuits under near-and sub-threshold supply voltages.

Exploration of high-speed 3.0 THz imaging with a 65 nm CMOS process

This paper describes a promising route for the exploration and development of 3.0 THz sensing and imaging with FET-based power detectors in a standard 65 nm CMOS process.Based on the plasma-wave theory proposed by Dyakonov and Shur,we designed high-responsivity and low-noise multiple detectors for monitoring a pulse-mode 3.0 THz quantum cascade laser(QCL).Furthermore,we present a fully integrated high-speed 32×32-pixel 3.0 THz CMOS image sensor(CIS).The full CIS measures 2.81×5.39 mm^(2) and achieves a 423 V/W responsivity(Rv)and a 5.3 nW integral noise equivalent power(NEP)at room temperature.In experiments,we demonstrate a testing speed reaching 319 fps under continuous-wave(CW)illumina-tion of a 3.0 THz QCL.The results indicate that our terahertz CIS has excellent potential in cost-effective and commercial THz imaging and material detection.

Energy-efficient reconfigurable AI processor

High computational energy-efficiency and rapid real-timeresponse are the major concerns for applications of artificial intelligencein low-power mobile and Internet of Things deviceswith limited storage capacity. Due to the outstanding superiorityof less memory requirement, low computation overheadand negligible accuracy degradation, deep neural networkswith binary/ternary weights (BTNNs) have been widely adoptedto replace traditional full-precision neural networks.

CMOS image sensors in ISSCC 2023

In IEEE International Solid-State Circuits Conference(ISSCC)2023,CMOS process is still the dominating fabrication technology for image sensors,and three-dimensional(3D)wafer-stacked process with Cu–Cu pixel-level connection has been adopted to achieve small pixel size and high integration level.The development of CMOS image sensors(CIS)is still focusing on the trends of high performance and more functionalities,such as hybrid event-based vision sensor(EVS)and terahertz(THz)/X-ray image sensor.

A Programmable High Speed Vision System with Superscalar PE and Its Parallel Computing Language

Pixel-parallel PE and SIMD architectures are widely used in high-speed image processing to enhance computing power. With fully exploiting the data level parallelism of low- and middle-level image processing, SIMD architecture is able to finish great amount of computation with much less instruction cycle thus satisfy the high-speed system requirement. The main computation parts in those SIMD image processing hardware is known as PE (processing element) and it is responsible for transferring, storing and processing the image data. This paper describes a high-speed vision system with superscalar PE to enhance system performance and its dedicated parallel computing language specifically devel-oped for this vision system. The vision system can achieve motion detection at more than 2000fps and face detection at more than 100 fps which overwhelms some general serial CPUs in the same applications.

A fast-locking bang-bang phase-locked loop with adaptive loop gain controller

This paper proposes a fast-locking bang-bang phase-locked loop（BBPLL）. A novel adaptive loop gain controller（ALGC） is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector（BBPFD） with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm;. Measured results show that the BBPLL operates at a frequency range from0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1μs @ 100 MHz frequency jump.The figure-of-merit of the fast-locking BBPLL is-334 dB.

High power-efficient asynchronous SAR ADC for IoT devices

This paper presents a power-efficient 100-MS/s,10-bit asynchronous successive approximation register（SAR） ADC.It includes an on-chip reference buffer and the total power dissipation is 6.8 mW.To achieve high performance with high power-efficiency in the proposed ADC,bootstrapped switch,redundancy,set-and-down switching approach,dynamic comparator and dynamic logic techniques are employed.The prototype was fabricated using 65 nm standard CMOS technology.At a 1.2-V supply and 100 MS/s,the ADC achieves an SNDR of 56.2 dB and a SFDR of 65.1 dB.The ADC core consumes only 3.1 mW,resulting in a figure of merit（FOM） of 30.27 fJ/conversionstep and occupies an active area of only 0.009 mm^2.