Radiation-hardened property of single-walled carbon nanotube film-based field-effect transistors under low-energy proton irradiation

Strong C-C bonds,nanoscale cross-section and low atomic number make single-walled carbon nanotubes(SWCNTs)a potential candidate material for integrated circuits(ICs)applied in outer space.However,very little work combines the simulation calculations with the electrical measurements of SWCNT field-effect transistors(FETs),which limits further understanding on the mechanisms of radiation effects.Here,SWCNT film-based FETs were fabricated to explore the total ionizing dose(TID)and displacement damage effect on the electrical performance under low-energy proton irradiation with different fluences up to 1×1015 p/cm2.Large negative shift of the threshold voltage and obvious decrease of the on-state current verified the TID effect caused in the oxide layer.The stability of the subthreshold swing and the off-state current reveals that the displacement damage caused in the CNT layer is not serious,which proves that the CNT film is radiation-hardened.Specially,according to the simulation,we found the displacement damage caused by protons is different in the source/drain contact area and channel area,leading to varying degrees of change for the contact resistance and sheet resistance.Having analyzed the simulation results and electrical measurements,we explained the low-energy proton irradiation mechanism of the CNT FETs,which is essential for the construction of radiation-hardened CNT film-based ICs for aircrafts.

Impact of symmetric gate-recess length on the DC and RF characteristics of InP HEMTs

We fabricated a set of symmetric gate-recess devices with gate length of 70 nm.We kept the source-to-drain spacing(L_(SD))unchanged,and obtained a group of devices with gate-recess length(L_(recess))from 0.4µm to 0.8µm through process improvement.In order to suppress the influence of the kink effect,we have done SiN_(X) passivation treatment.The maximum saturation current density(ID_(max))and maximum transconductance(g_(m,max))increase as L_(recess) decreases to 0.4µm.At this time,the device shows ID_(max)=749.6 mA/mm at V_(GS)=0.2 V,V_(DS)=1.5 V,and g_(m,max)=1111 mS/mm at V_(GS)=−0.35 V,V_(DS)=1.5 V.Meanwhile,as L_(recess) increases,it causes parasitic capacitance C_(gd) and g_(d) to decrease,making f_(max) drastically increases.When L_(recess)=0.8µm,the device shows f_(T)=188 GHz and f_(max)=1112 GHz.

Impact of gate offset in gate recess on DC and RF performance of InAlAs/InGaAs InP-based HEMTs

A set of 100-nm gate-length In P-based high electron mobility transistors(HEMTs)were designed and fabricated with different gate offsets in gate recess.A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography.DC and RF measurement was conducted.With the gate offset varying from drain side to source side,the maximum drain current(I_(ds,max))and transconductance(g_(m,max))increased.In the meantime,fTdecreased while f;increased,and the highest fmax of 1096 GHz was obtained.It can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source resistance.Output conductance was also suppressed by gate offset toward source side.This provides simple and flexible device parameter selection for HEMTs of different usages.