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Morphological and molecular basis of ovarian serous carcinoma
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作者 Daniel G Rosen Zhihong Zhang +1 位作者 weiwei shan Jmsong Liu 《The Journal of Biomedical Research》 CAS 2010年第4期257-263,共7页
Serous carcinoma is the most common type of epithelial ovarian cancer. In this review, we provide a com- prehensive picture of ovarian serous cancers from multiple aspects: the first part of this review summarizes th... Serous carcinoma is the most common type of epithelial ovarian cancer. In this review, we provide a com- prehensive picture of ovarian serous cancers from multiple aspects: the first part of this review summarizes the morphological, histological, and immunological signatures of ovarian serous carcinoma; subsequently, we review the history of the evolvement of different grading systems used in ovarian serous cancer; in the end, we focus on characterizing the genetics that underlie the 2-tiered pathways through which ovarian serous cancers are believed to arise: the low-grade and the high-grade pathways. 展开更多
关键词 ovarian carcinoma GRADING MORPHOLOGY molecular genetics TUMORIGENESIS
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面向高性能计算的低温芯片技术:发展和挑战
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作者 程然 李博 +5 位作者 王宗巍 张结印 单伟伟 张建军 蔡一茂 韩根全 《中国科学:信息科学》 CSCD 北大核心 2024年第1期88-101,共14页
过去60多年,集成电路技术的进步推动了电子信息领域的快速发展.随着工艺制程进入纳米阶段,通过微缩化技术进一步提升器件和电路的性能需要克服技术和成本方面的多重挑战.探寻新的器件、设计和架构技术是高性能计算领域解决当下瓶颈的必... 过去60多年,集成电路技术的进步推动了电子信息领域的快速发展.随着工艺制程进入纳米阶段,通过微缩化技术进一步提升器件和电路的性能需要克服技术和成本方面的多重挑战.探寻新的器件、设计和架构技术是高性能计算领域解决当下瓶颈的必然路径.低温芯片技术,利用晶体管低温下电学性能的提升,可以进一步提高逻辑芯片的算力并降低动态和静态功耗,由于和现有集成电路技术兼容性较高,是低成本实现更高性能计算的理想技术路线之一.此外,随着量子计算技术的发展,可扩展的大规模量子芯片需要和极低温互补金属氧化物半导体CMOS电路以及存储芯片实现片上集成,进而实现更高效的数据处理.本文面向高性能计算应用,从器件表征、模型、仿真和设计、应用等多个层面,分析并总结了低温芯片技术领域的发展历程、理论基础和技术挑战,并给出针对性的解决方案和建议,有助于推动我国在低温芯片技术领域的持续发展. 展开更多
关键词 低温芯片 低温电子学 低温PDK 高性能计算 量子计算
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Near-Threshold Wide-Voltage Design Review
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作者 Yan Zhao Jun Yang +5 位作者 Chao Chen weiwei shan Peng Cao Yongliang Zhou Ziyu Li Tai Yang 《Tsinghua Science and Technology》 SCIE EI CAS CSCD 2023年第4期696-718,共23页
This paper presents a comprehensive review of near-threshold wide-voltage designs on memory,resilient logic designs,low voltage Radio Frequency(RF)circuits,and timing analysis.With the prosperous development of wearab... This paper presents a comprehensive review of near-threshold wide-voltage designs on memory,resilient logic designs,low voltage Radio Frequency(RF)circuits,and timing analysis.With the prosperous development of wearable applications,low power consumption has become one of the primary challenges for IC designs.To improve the power efficiency,the prefer scheme is to operate at an ultra low voltage of Near Threshold Voltage(NTV).For the performance variation and degradation,a self-adaptive margin assignment technique is proposed in the low voltage.The proposed technique tracks the circuit states in real time and dynamically allocates voltage margins,reducing the minimum supply voltage and achieving higher energy efficiency.The self-adaptive margin assignment technique can be used in Static Random Access Memory(SRAM),digital circuits,and analog/RF circuits.Based on the self-adaptive margin assignment technique,the minimum voltage in the 40 nm CMOS process is reduced to 0.6 V or even lower,and the energy efficiency is increased by 3–4 times. 展开更多
关键词 Near Threshold Voltage(NTV) wide-voltage memory resilient logic design low voltage Radio Frequency(RF) timing analysis
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