集成电路设计与集成系统专业培养方案的研究——以华中科技大学为例

国家为鼓励和支持我国集成电路产业发展,连续出台了一系列文件。针对国家急缺集成电路方向人才的现状,华中科技大学自2009年开办集成电路设计与集成系统本科专业。开办之初,以国内众多高校建设该专业的经验为高起点,确定了集成电路设计与集成系统本科专业的建设原则,在广泛调研了国内外相关专业培养方案之后,制订了独具特色的培养方案。文章还以体系结构及嵌入式系统知识点为例,给出了相关课程和授课内容。总结10年来的专业建设成果和经验,该培养方案得到各高校和用人单位高度认可。

An analog front-end circuit for ISO/IEC 15693-compatible RFID transponder IC

The 13.56 MHz analog front-end circuit for ISO/IEC 15693-compatible radio frequency identification (RFID) trans- ponder IC presented in this paper converts RF power to DC and extracts clock and data from the interrogator by 10% or 100% ASK modulation. The transponder sends data back to the interrogator by load modulation technology. The electrostatic discharge (ESD) protection circuits function to limit RF voltage to a safe level. An inductive coupling simulation modelling for 13.56 MHz RFID system is presented, with simulation results showing that the transponder operates over a wide range of electromagnetic field strength from Hmin (150 mA/m) to Hmax (5 A/m). The transponder IC is implemented in SMIC 0.35-μm three-metal two-poly mixed signal CMOS technology with embedded EEPROM.

A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic

Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.

一块用于V2X通信的国密安全芯片设计与验证

随着车联网的不断发展,人们对车联网系统的安全性也提出了更高的要求。为了保护用户的隐私和人身安全,需要采用加解密算法对车联网通信进行保护。在中国,国密算法是被广泛采用的一种加解密算法,因此,本文设计了一块支持SM2、SM3、SM4算法,用于车联网场景的安全芯片,同时兼容RSA和ECC算法,完成了仿真及FPGA验证并使用55nm工艺库进行了流片。电路总面积为3.98mm2,约1.2×106个MOS管,外设最高工作频率为200MHz,可在2.14M时钟周期内完成一次257位二元扩域点乘运算,具有较高的面积利用率和兼容性。

A 155 Mbps laser diode driver with automatic power and extinction ratio control

An integrated laser diode driver(LDD) driving an edge-emitting laser diode was designed and fabricated by 0.35 μm BiCMOS technology. This paper proposes a scheme which combines the automatic power control loop and temperature com-pensation for modulation current in order to maintain constant extinction ratio and average optical power. To implement tem-perature compensation for modulation current,a novel circuit which generates a PTAT current by using the injecting base current of a bipolar transistor in saturation region,and alternates the amplifier feedback loop(closed or not) to control the state of the current path is presented. Simulation results showed that programmed by choice of external resistors,the IC can provide modu-lation current from 5 mA to 85 mA with temperature compensation adjustments and independent bias current from 4 mA to 100 mA. Optical test results showed that clear eye-diagrams can be obtained at 155 Mbps,with the output optical power being nearly constant,and the variation of extinction ratio being lower than 0.7 dB.

A Super Performance Bandgap Voltage Reference with Adjustable Output for DC-DC Converter

This paper presents a super performance bandgap voltage reference for DC-DC converter with adjustable output. it generates a wide range of voltage reference ranging from sub- 1V to 1,221 7 V and has a low temperature coefficient of 2.3 × 10 ^5/K over the temperature variation using the current feedback and resistive subdivision. In addition, the power supply rejection ration of the proposed bandgap voltage reference is 78 dB. When supply voltage varies from 2.5 V to 6 V, output VREF is 1,221 685±0.055 mV.

S-Mesh: a Mesh-based on-chip network with separation of control and transmission

The current network-on-chip （NoC） topology cannot predict subsequent switch node status promptly. Switch nodes have to perform various functions such as routing decision, data forwarding, packet buffering, congestion control and properties of an NoC system. Therefore, these make switch architecture far more complex. This article puts forward a separating on-chip network architecture based on Mesh （S-Mesh）, S-Mesh is an on-chip network that separates routing decision flow from the switches. It consists of two types of networks： datapath network （DN） and control network （CN）. The CN establishes data paths for data transferring in DN. Meanwhile, the CN also transfers instructions between different resources. This property makes switch architecture simple, and eliminates conflicts in network interface units between the resource and switch. Compared with 2D-Mesh, Toms Mesh, Fat-tree and Butterfly, the average packet latency in S-Mesh is the shortest when the packet length is more than 53 B. Compared with 2D-Mesh, the areas savings of S-Mesh is about 3%-7/% and the power dissipation is decreased by approximate 2%.

Design of highly efficient elliptic curve crypto-processor with two multiplications over GF(2^(163))

In this article, a parallel hardware processor is presented to compute elliptic curve scalar multiplication in polynomial basis representation. The processor is applicable to the operations of scalar multiplication by using a modular arithmetic logic unit （MALU）. The MALU consists of two multiplications, one addition, and one squaring. The two multiplications and the addition or squaring can be computed in parallel. The whole computations of scalar multiplication over GF（2^163） can be performed in 3 064 cycles. The simulation results based on Xilinx Virtex2 XC2V6000 FPGAs show that the proposed design can compute random GF（2^163） elliptic curve scalar multiplication operations in 31.17 μs, and the resource occupies 3 994 registers and 15 527 LUTs, which indicates that the crypto-processor is suitable for high-performance application.

Preparation of a new gate dielectric material HfTiON film

A new gate dielectric material HfTiON is deposited by reactive co-sputtering of Hf and Ti targets in N2/O2 ambient, followed by annealing in N2 at 600 ℃ and 800 ℃ respectively for 2 min. Capacitance-voltage and gate-leakage properties are characterized and compared for different anneal conditions. The results indicate that the sample annealed at 800 ℃ exhibits lower interface-state and oxide-charge densities, and better device reliability. This is attributed to the fact that the rapid thermal annealing at the higher temperature of 800 ℃ can effectively remove the damage-induced precipitation, forming a hardened dielectric/Si interface with high reliability.