Design of GGNMOS ESD protection device for radiationhardened 0.18 μm CMOS process

In this paper,the ESD discharge capability of GGNMOS(gate grounded NMOS)device in the radiation-hardened 0.18μm bulk silicon CMOS process(Rad-Hard by Process:RHBP)is optimized by layout and ion implantation design.The effects of gate length,DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation.The size of DCGS,multi finger number and single finger width of ESD verification structures are designed,and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology.Finally,the optimized GGNMOS is verified on the DSP circuit,and its ESD performance is over 3500 V in HBM mode.

A High-Linear Radio Frequency Quadrature Modulator with Improved Sideband Suppression and Carrier Leakage Performance

The quadrature modulator is a crucial block in transmitters that upconverts baseband signals to theRadio Frequency(RF)band of interest using local oscillator frequencies.In this paper,non-ideal factors thatinfluence the performance of the quadrature modulator are considered,and solutions are accordingly taken inthe quadrature modulator design.A high-linear RF quadrature modulator with improved sideband suppressionand carrier leakage performance is presented in this work.The quadrature modulator implemented in the0.18-μm SiGe process uses the current bleeding technique to improve the general performance of the doublebalanced active Gilbert mixers.An on-chip prescaler followed by two cascaded limiting amplifiers is designed toprovide accurate quadrature local oscillator signals.Predrivers at quadrature baseband signal input ports areproposed to eliminate DC offsets.The measured sideband suppression achieves a performance of better than−43 dBc and carrier leakage is less than−38 dBm over the output RF frequency range of 30 MHz to 2.15 GHz.The output 1 dB compression point equals 11.4 dBm at 800 MHz.

A 12-bit 250-MS/s Charge-Domain Pipelined Analog-to-Digital Converter with Feed-Forward Common-Mode Charge Control

A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.

Design of Low-Power Modern Radar SoC Based on ASIX

With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip （SoC） based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18-μm 1P6M Salicide CMOS process, the area is 7.825 mm x 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.

A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC

A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode （CM） output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a serial data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1.8 V 1PSM CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5 × 3.2 mm2, where the active area of the transmitter block is 0.5× 1.2 mm2.