This study investigates the carrier transport of heterojunction channel in oxide semiconductor thin-film transistor(TFT)using the elevated-metal metal-oxide(EMMO)architecture and indium−zinc oxide(InZnO).The heterojun...This study investigates the carrier transport of heterojunction channel in oxide semiconductor thin-film transistor(TFT)using the elevated-metal metal-oxide(EMMO)architecture and indium−zinc oxide(InZnO).The heterojunction band diagram of InZnO bilayer was modified by the cation composition to form the two-dimensional electron gas(2DEG)at the interface quantum well,as verified using a metal−insulator−semiconductor(MIS)device.Although the 2DEG indeed contributes to a higher mobility than the monolayer channel,the competition and cooperation between the gate field and the built-in field strongly affect such mobility-boosting effect,originating from the carrier inelastic collision at the heterojunction interface and the gate field-induced suppression of quantum well.Benefited from the proper energy-band engineering,a high mobility of 84.3 cm2·V^(−1)·s^(−1),a decent threshold voltage(V_(th))of−6.5 V,and a steep subthreshold swing(SS)of 0.29 V/dec were obtained in InZnO-based heterojunction TFT.展开更多
针对背沟道刻蚀(Back Channel Etch,BCE)技术的非晶铟镓锌氧化物(a-IGZO)薄膜晶体管(Thin Film Transistor,TFTs),建立了一种高浓度掺杂态密度模型(High Concentration Doping Density Of States model,HCD-DOS model),并通过数值模拟...针对背沟道刻蚀(Back Channel Etch,BCE)技术的非晶铟镓锌氧化物(a-IGZO)薄膜晶体管(Thin Film Transistor,TFTs),建立了一种高浓度掺杂态密度模型(High Concentration Doping Density Of States model,HCD-DOS model),并通过数值模拟研究态密度关键参数对器件性能的影响,以此揭示a-IGZO TFTs中制备工艺对导电沟道修复的物理机理.首先,采用结合强度较高的钼/铜双层结构作为栅/源/漏电极,引入BCE方法制备了底栅顶接触(BottomGate Top-Contact,BG-TC)TFTs.其次,建立了适用于BCE技术的a-IGZO TFTs的HCD-DOS模型.随后,基于TCAD(Technology Computer Aided Design)仿真器对态密度关键参数进行数值研究,结果表明,不同态密度参数对a-IGZO TFTs器件转移特性曲线、电学特性以及沟道内部电子浓度分布的影响有所差异.最后,基于HCD-DOS模型探索SiO_(x)钝化层沉积和N_(2)O等离子体处理对器件内部机理的影响.研究发现,N2O等离子体处理对态密度分布和沟道载流子浓度有显著影响,进而导致阈值电压正向漂移.展开更多
The conventional computing architecture faces substantial chal-lenges,including high latency and energy consumption between memory and processing units.In response,in-memory computing has emerged as a promising altern...The conventional computing architecture faces substantial chal-lenges,including high latency and energy consumption between memory and processing units.In response,in-memory computing has emerged as a promising alternative architecture,enabling computing operations within memory arrays to overcome these limitations.Memristive devices have gained significant attention as key components for in-memory computing due to their high-density arrays,rapid response times,and ability to emulate biological synapses.Among these devices,two-dimensional(2D)material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing,thanks to their exceptional performance driven by the unique properties of 2D materials,such as layered structures,mechanical flexibility,and the capability to form heterojunctions.This review delves into the state-of-the-art research on 2D material-based memristive arrays,encompassing critical aspects such as material selection,device perfor-mance metrics,array structures,and potential applications.Furthermore,it provides a comprehensive overview of the current challenges and limitations associated with these arrays,along with potential solutions.The primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing,leveraging the potential of 2D material-based memristive devices.展开更多
基金supported by National Key Research and Development Program(2021YFB3600802)Shenzhen Municipal Scientific Program(JSGG20220831103803007,SGDX20211123145404006)Guangdong Basic and Applied Basic Research Foundation(2022A1515110029)
文摘This study investigates the carrier transport of heterojunction channel in oxide semiconductor thin-film transistor(TFT)using the elevated-metal metal-oxide(EMMO)architecture and indium−zinc oxide(InZnO).The heterojunction band diagram of InZnO bilayer was modified by the cation composition to form the two-dimensional electron gas(2DEG)at the interface quantum well,as verified using a metal−insulator−semiconductor(MIS)device.Although the 2DEG indeed contributes to a higher mobility than the monolayer channel,the competition and cooperation between the gate field and the built-in field strongly affect such mobility-boosting effect,originating from the carrier inelastic collision at the heterojunction interface and the gate field-induced suppression of quantum well.Benefited from the proper energy-band engineering,a high mobility of 84.3 cm2·V^(−1)·s^(−1),a decent threshold voltage(V_(th))of−6.5 V,and a steep subthreshold swing(SS)of 0.29 V/dec were obtained in InZnO-based heterojunction TFT.
文摘针对背沟道刻蚀(Back Channel Etch,BCE)技术的非晶铟镓锌氧化物(a-IGZO)薄膜晶体管(Thin Film Transistor,TFTs),建立了一种高浓度掺杂态密度模型(High Concentration Doping Density Of States model,HCD-DOS model),并通过数值模拟研究态密度关键参数对器件性能的影响,以此揭示a-IGZO TFTs中制备工艺对导电沟道修复的物理机理.首先,采用结合强度较高的钼/铜双层结构作为栅/源/漏电极,引入BCE方法制备了底栅顶接触(BottomGate Top-Contact,BG-TC)TFTs.其次,建立了适用于BCE技术的a-IGZO TFTs的HCD-DOS模型.随后,基于TCAD(Technology Computer Aided Design)仿真器对态密度关键参数进行数值研究,结果表明,不同态密度参数对a-IGZO TFTs器件转移特性曲线、电学特性以及沟道内部电子浓度分布的影响有所差异.最后,基于HCD-DOS模型探索SiO_(x)钝化层沉积和N_(2)O等离子体处理对器件内部机理的影响.研究发现,N2O等离子体处理对态密度分布和沟道载流子浓度有显著影响,进而导致阈值电压正向漂移.
基金This work was supported by the National Research Foundation,Singapore under Award No.NRF-CRP24-2020-0002.
文摘The conventional computing architecture faces substantial chal-lenges,including high latency and energy consumption between memory and processing units.In response,in-memory computing has emerged as a promising alternative architecture,enabling computing operations within memory arrays to overcome these limitations.Memristive devices have gained significant attention as key components for in-memory computing due to their high-density arrays,rapid response times,and ability to emulate biological synapses.Among these devices,two-dimensional(2D)material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing,thanks to their exceptional performance driven by the unique properties of 2D materials,such as layered structures,mechanical flexibility,and the capability to form heterojunctions.This review delves into the state-of-the-art research on 2D material-based memristive arrays,encompassing critical aspects such as material selection,device perfor-mance metrics,array structures,and potential applications.Furthermore,it provides a comprehensive overview of the current challenges and limitations associated with these arrays,along with potential solutions.The primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing,leveraging the potential of 2D material-based memristive devices.
