利用变量节点符号可靠度在迭代过程中的分布特征,提出了一种基于可靠度差值特征的自适应判决多元低密度奇偶校验(Low Density Parity Check, LDPC)译码算法。整个迭代过程划分为两个阶段,针对不同阶段节点可靠度的差值特征分别采用不同...利用变量节点符号可靠度在迭代过程中的分布特征,提出了一种基于可靠度差值特征的自适应判决多元低密度奇偶校验(Low Density Parity Check, LDPC)译码算法。整个迭代过程划分为两个阶段,针对不同阶段节点可靠度的差值特征分别采用不同的判决策略:前期阶段,采用传统的基于最大可靠度的判决策略;后期阶段,根据最大、次大可靠度之间的差值特征,设计自适应的码元符号判决策略。仿真结果表明,所提算法在相当的译码复杂度前提下,能获得0.15~0.4 dB的性能增益。同时,对于列重较小的LDPC码,具有更低的译码错误平层。展开更多
研究了在数据无损压缩领域影响深远的两种压缩算法 :L Z78及 L Z77,提出了一种改进的混合字典压缩算法 HL Z(Hybrid L Z) .HL Z是基于 L Z78和 L Z77的一种混合算法 ,利用了 L Z78和 L Z77的互补特性 .在用 HL Z算法进行正文编码时 ,当...研究了在数据无损压缩领域影响深远的两种压缩算法 :L Z78及 L Z77,提出了一种改进的混合字典压缩算法 HL Z(Hybrid L Z) .HL Z是基于 L Z78和 L Z77的一种混合算法 ,利用了 L Z78和 L Z77的互补特性 .在用 HL Z算法进行正文编码时 ,当发现已经到达字典中提供的词汇终点时 ,并不立刻进行编码 ,而是与滑动窗口相比较 ,若当前字符串在滑动窗口中的匹配长度尚不及它在字典中的匹配串的长度 ,则采用 L Z78输出 ,否则用 L Z77编码输出 .在还原输出编码时 ,HL Z算法建立了一个链结构 ,将字典中具有相同首字母的词条链接起来 ,大大减少了搜索字典中对应最长匹配串的时间 .实验结果表明 ,HL Z算法具有与 L Z78和 L Z77相似的计算复杂度和存储复杂度 ,但具有更好的全局与局部自适应性、更高的压缩效率 .展开更多
In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline ar...In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox in the AES algorithm is optimized. ShiftRow and MixColumn, which are the main components in AES round transformation, are optimized with the reconfigurable technology. The design is implemented on the Xilinx Virtex2p xc2vp20-7 field programmable gate array （FPGA） device. It can achieve a data throughput above 2.58 Gbit/s, and it only requires 3 233 slices. Compared with other related designs of AES IP cores on the same device, the proposed design can achieve a tradeoff between speed and area, and obtain satisfactory results in both data throughput and hardware resource consumption.展开更多
文摘研究了在数据无损压缩领域影响深远的两种压缩算法 :L Z78及 L Z77,提出了一种改进的混合字典压缩算法 HL Z(Hybrid L Z) .HL Z是基于 L Z78和 L Z77的一种混合算法 ,利用了 L Z78和 L Z77的互补特性 .在用 HL Z算法进行正文编码时 ,当发现已经到达字典中提供的词汇终点时 ,并不立刻进行编码 ,而是与滑动窗口相比较 ,若当前字符串在滑动窗口中的匹配长度尚不及它在字典中的匹配串的长度 ,则采用 L Z78输出 ,否则用 L Z77编码输出 .在还原输出编码时 ,HL Z算法建立了一个链结构 ,将字典中具有相同首字母的词条链接起来 ,大大减少了搜索字典中对应最长匹配串的时间 .实验结果表明 ,HL Z算法具有与 L Z78和 L Z77相似的计算复杂度和存储复杂度 ,但具有更好的全局与局部自适应性、更高的压缩效率 .
文摘In order to improve the data throughput of the advanced encryption standard （AES） IP core while reducing the hardware resource consumption and finally achieving a tradeoff between speed and area, a mixed pipeline architecture and reconfigurable technology for the design and implementation of the AES IP core is proposed. The encryption and decryption processes of the AES algorithm are achieved in the same process within the mixed pipeline structure. According to the finite field characterizations, the Sbox in the AES algorithm is optimized. ShiftRow and MixColumn, which are the main components in AES round transformation, are optimized with the reconfigurable technology. The design is implemented on the Xilinx Virtex2p xc2vp20-7 field programmable gate array （FPGA） device. It can achieve a data throughput above 2.58 Gbit/s, and it only requires 3 233 slices. Compared with other related designs of AES IP cores on the same device, the proposed design can achieve a tradeoff between speed and area, and obtain satisfactory results in both data throughput and hardware resource consumption.
