Design and Analysis of Analog Front-End of Passive RFID Transponders

An analog front-end of HF passive RFID transponders compatible with ISO/IEC 18000-3 is presented.Design considerations, especially the power transmission in the RFID transponder, are analyzed. Based on these considerations,an analog front-end is presented with novel architecture, high power conversion efficiency, low voltage, low power consumption, and high performance in an environment of noise and power fluctuation. The circuit is implemented in a Chartered 0.35μm standard CMOS process. The experimental results show that the chip can satisfy the design target well.

Analysis and Design of a Low-Cost RFID Tag Analog Front-End

A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly reduced. Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented. The circuit is implemented in an SMIC 0.18μm EEPROM process. Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%. For a sinusoidal wave with magnitude of 0. 5V, the output DC voltage reaches IV,which is high enough for RFID tags. The read distance is as far as 22cm.

An analog front-end circuit for ISO/IEC 15693-compatible RFID transponder IC

The 13.56 MHz analog front-end circuit for ISO/IEC 15693-compatible radio frequency identification (RFID) trans- ponder IC presented in this paper converts RF power to DC and extracts clock and data from the interrogator by 10% or 100% ASK modulation. The transponder sends data back to the interrogator by load modulation technology. The electrostatic discharge (ESD) protection circuits function to limit RF voltage to a safe level. An inductive coupling simulation modelling for 13.56 MHz RFID system is presented, with simulation results showing that the transponder operates over a wide range of electromagnetic field strength from Hmin (150 mA/m) to Hmax (5 A/m). The transponder IC is implemented in SMIC 0.35-μm three-metal two-poly mixed signal CMOS technology with embedded EEPROM.

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.

Multi-frequency point supported LLRF front-end for CiADS wide-bandwidth application

The China initiative Accelerator Driven System,CiADS,physics design adopts 162.5 MHz,325 MHz,and 650 MHz cavities,which are driven by the corresponding radio frequency(RF)power system,requiring frequency translation front-end for the RF station.For that application,a general-purpose design front-end prototype has been developed to evaluate the multi-frequency point supported design feasibility.The difficult parts to achieve the requirements of the general-purpose design are reasonable device selection and balanced design.With a carefully selected low-noise wide-band RF mixer and amplifier to balance the performance of multi-frequency supported down-conversion,specially designed LO distribution net to increase isolation between adjacent channels,and external band-pass filter to realize expected up-conversion frequencies,high maintenance and modular front-end generalpurpose design has been implemented.Results of standard parameters show an R2 value of at least 99.991%in the range of-60-10 dBm for linearity,up to 18 dBm for P1dB,and up to 89 dBc for cross talk between adjacent channels.The phase noise spectrum is lower than 80 dBc in the range of 0-1 MHz;cumulative phase noise is 0.006°;and amplitude and phase stability are 0.022%and 0.034°,respectively.

Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer

A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.

Advances in Digital Front-End and Software RF Processing: PartⅡ

In the first editorial of this two-part special issue, we pointed out that one of the biggest trends in wireless broadband, radar, sonar, and broadcasting technology is software RF processing and digital front-end [1]. Thistrend encompasses signal processing algorithms and integrated circuit design and includes digital pre-distortion （DPD）, conversions between digital and analog signals, digita up-conversion （DUC）, digital down-conversion （DDC）, DC offset,

Advances in Digital Front-End and Software RF Processing:Part I

One of the biggest technology trends in wireless broadband, radar, sonar, and broadcasting systems is software radio frequency processing and digital front-end. This trend encompasses a broad range of topics, from circuit design and signal processing to system integration. It includes digital up-conversion （DUC） and down-conversion （DDC）, digital predistortion （DPD）,

Reconfigurable Ultrasonic Testing System Development Using Programmable Analog Front-End and Reconfigurable System-on-Chip Hardware

Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.

高频RFID读写器射频模拟前端的实现

射频识别(RFID)系统主要由RFID读写器和RFID电子标签两部分组成。给出了高频(13.56MHz)RFID系统中读写器射频模拟前端的电路设计,符合ISO/IEC14443typeA/typeB,ISO/IEC15693和ISO/IEC18000-3中任一个标准的读写器芯片设计均可采用,设计工艺采用了中芯国际0.35μm2P3M混合CMOS技术,并给出了Cadence环境下的仿真结果。

UHF RFID读写器射频前端电路设计

RFID近年来发展迅速,广泛应用在物流、交通、军事等领域。在研究RFID读写器设计的基础上,提出了符合EPCClass-1,Generation-2标准的UHF RFID读写器射频前端的电路设计方案,着重设计了射频前端中频滤波模块和低噪声放大模块的电路。电路设计基于0.18μmCMOS工艺标准的单元库,采用EDA工具对电路进行了性能分析。仿真结果表明中频滤波模块和低噪声放大模块性能良好,符合EPC Class-1,Generation-2标准。

915MHz超高频RFID阅读器射频前端电路设计

为了提高超高频RFID系统中阅读器在低信噪比的情况下仍具有较高的识别能力,提出一种基于FPGA系统结合软件无线电方法实现超高频RFID射频前端电路方案。超高频射频识别系统必须符合EPC Class 1generation 2标准,所设计的电路系统以Xilinx公司的XC6SLX16-2CSG324FPGA芯片为硬件基础,将数字基带调制解调和中频滤波电路在FPGA系统中设计实现,重点阐述了射频前端电路的设计结构、AD/DA转换电路,以及数字滤波器的设计。实验结果表明,所设计的超高频RFID阅读器简化了前端电路系统结构,提升了稳定性,增强了抗干扰能力。该电路系统在信噪比较低的情况下,能够较好地实现915MHz频率的射频接收和发送。

基于FPGA与AD/DA的JESD204B协议通信与控制模块设计

为了完成高速射频信号的采集与发射,设计了基于FPGA、模数转换器AD9680与数模转换器AD9144电路的通信与控制模块。硬件设计主要包含前端设计、时钟设计、控制部分设计。软件部分则详细阐述了程序结构、模块设计以及程序执行流程。为兼容各种不同的AD/DA芯片且便于移植复用,所有数据处理以及寄存器配置都在FPGA的处理系统(PS)部分完成,在可编程逻辑(PL)部分完成与PS以及外设的数据交互与存储。该软件整体可视作一个软件封装IP。使用FPGA为主控芯片与AD/DA完成10 Gbit/s的线速率JESD204B链路通信,并以2 GSa/s的转换速率进行数据采集与发射,验证了设计的正确性。

基于WPEE-RF的模拟电路故障诊断

为实现高效的模拟电路故障诊断,提出了基于小波包能量熵(WPEE)和随机森林(RF)的模拟电路故障诊断方法;选择合适的测试激励信号,监测电路收集数据,对模拟电路监测数据进行5层小波包分解,计算多频带WPEE向量表征故障特征,由RF分类器实现故障诊断;仿真实验结果表明,该方法在双二次滤波电路、Sallen-key滤波电路容差故障诊断以及对数放大器综合故障诊断中体现出良好的性能,故障诊断准确率达99%以上,且该方法具有参数鲁棒性,RF模型训练时间短;较支持向量机和BP网络方法相比,表现出更好的综合性能,更能贴近工程实践应用。

A tunable passive mixer for SAW-less front-end with reconfigurable voltage conversion gain and intermediate frequency bandwidth

An adjustable mixer for surface acoustic wave( SAW)-less radio frequency( RF) front-end is presented in this paper. Through changing the bias voltage,the presented mixer with reconfigurable voltage conversion gain( VCG) is suitable for multi-mode multi-standard( MMMS) applications. An equivalent local oscillator( LO) frequency-tunable high-Q band-pass filter( BPF) at low noise amplifier( LNA) output is used to reject the out-of-band interference signals. Base-band( BB) capacitor of the mixer is variable to obtain 15 kinds of intermediate frequency( IF) bandwidth( BW). The proposed passive mixer with LNA is implemented in TSMC 0. 18μm RF CMOS process and operates from 0. 5 to 2. 5 GHz with measured maximum out-of-band rejection larger than 40 d B. The measured VCG of the front-end can be changed from 5 to 17 d B; the maximum input intercept point( IIP3) is0 d Bm and the minimum noise figure( NF) is 3. 7 d B. The chip occupies an area of 0. 44 mm^2 including pads.

Spectre X RF在大规模RFIC设计中的应用

随着工艺尺寸的不断缩小,电路规模的不断复杂化以及版图中寄生规模的不断增大,在一些大规模的后仿验证过程中,Cadence公司提供的模拟全精度仿真器Spectre/APS/APS RF已不能满足需求。针对这一问题,Cadence于2019年推出APS的下一代模拟全精度仿真器Spectre X,在实际使用过程中发现其对普通模拟仿真性能提升明显并且基本保持了APS的仿真精度。2020年,Cadence推出其APS RF的下一代仿真器Spectre X RF仿真器。RF仿真在整体仿真验证流程中同样占据很大一部分,在将其应用到实际项目前,需要与APS RF对比其性能和速度。介绍了Spectre X RF的用法,并重点介绍在几种采用不同工艺的RFIC设计中,仿真器Spectre APS RF与Spectre X RF仿真性能与精度的对比情况。

Optimization and Synthesis of RF CMOS Polyphase Filters with Layout Considerations

A novel software tool for optimization and synthesis of RF CMOS polyhase filters(PPFs),PPFOPTIMA,is developed.In the optimization engine,genetic algorithm is adopted to avoid local optima.Experiments on PPFOPTIMA demonstrate that it is an efficient design aid for design and optimization of RF CMOS PPFs.

Design Consideration in the Development of Multi-Fin FETs for RF Applications

In this paper, we propose multi-fin FET design techniques targeted for RF applications. Overlap and underlap design configuration in a base FinFET are compared first and then multi-fin device (consisting of transistor unit up to 50) is studied to develop design limitations and to evaluate their effects on the device performance. We have also investigated the impact of the number of fins (up to 50) in multi-fin structure and resulting RF parameters. Our results show that as the number of fin increases, underlap design compromises RF performance and short channel effects. The results provide technical understanding that is necessary to realize new opportunities for RF and analog mixed-signal design with nanoscale FinFETs.

ADI推出的RF设计工具现已支持Hittite微波产品

Analog Devices,Inc.（ADI）,全球领先的高性能信号处理解决方案和RF IC供应商,最近在北京发布了广受欢迎的RF设计工具,支持ADI Hittite微波公司的产品。ADI sim RF TM设计工具让工程师可以通过ADI的RF IC产品组合对RF和微波信号链建模。ADI sim RF Version 1.9增加了190款混频器、放大器、开关和衰减器,其中大部分来自Hittite的产品组合。

射频功放建模及数字预失真算法仿真实验

该文主要研究射频功放建模及数字预失真(digital pre-distortion,DPD)算法。首先,对射频功放的基本特性和DPD系统装置进行介绍。然后,根据各类装置的优劣进行选择,在MATLAB平台上搭建射频功放模型,并选择相适配的DPD装置。最后,观察DPD算法对整个通信系统的线性度改善情况,评价指标包括功率谱图、SNR-误码率图、幅度-幅度(AM-AM)效应图、幅度-相位(AM-PM)效应图、星座图和功率谱密度图。该研究成果可用于提升5G通信中频谱资源的利用效率,也可用于相关专业的实验教学。