A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces...A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces the precharge operations of the video processing unit in one access; adaptive- precharge avoids unnecessary precharge operations; while command interleaving inserts the precharge and activate commands of the next access into the command sequence of the current access, thus reduces the no operation （NOP） cycles. Combination of these three schemes effectively improves the SDRAM performance. Compared with precharge-all scheme, adaptive-precharge and command interleaving reduce the SDRAM overhead cycles by 70% and increases SDRAM performance by up to 19.2% in the best case. This controller has been implemented in an AVS SoC and the frequency is 200MHz.展开更多
This paper describes the method of built-in self-repairing of RAM on board, designs hardware circuit, and logic for the RAM's faults self-repairing system based on FPGA. The key technology is that it utilizes FPGA...This paper describes the method of built-in self-repairing of RAM on board, designs hardware circuit, and logic for the RAM's faults self-repairing system based on FPGA. The key technology is that it utilizes FPGA to test RAM according to some algorithm to find out failure memory units and replace the faulty units with FPGA. Then it can build a memory that has no fault concern to external controller, and realizes the logic binding between external controller and RAM. Micro Controller Unit (MCU) can operate external RAM correctly even if RAM has some fault address units. Conventional MCS-51 is used to simulate the operation of MCU operating external memory. Simulation shows FPGA can complete the faulty address units' mapping and MCU can normally read and write external RAM. This design realizes the RAM's built-in self-repairing on board.展开更多
Stateless translation and stateless double translation/encapsulation technologies （IVI/MAP-T/MAP-E） define the address mapping and protocol translation/encapsulation algorithms between IPv4 and IPv6. IVI/MAP-T/MAP-E...Stateless translation and stateless double translation/encapsulation technologies （IVI/MAP-T/MAP-E） define the address mapping and protocol translation/encapsulation algorithms between IPv4 and IPv6. IVI/MAP-T/MAP-E technologies maintain end-to-end address transparency between IPvd and IPv6 and support communication initiated by IPv4-only or IPv6-only end systems. Therefore, they are the very critical techniques for the IPv4/IPv6 coexistence and transition.展开更多
文摘A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces the precharge operations of the video processing unit in one access; adaptive- precharge avoids unnecessary precharge operations; while command interleaving inserts the precharge and activate commands of the next access into the command sequence of the current access, thus reduces the no operation （NOP） cycles. Combination of these three schemes effectively improves the SDRAM performance. Compared with precharge-all scheme, adaptive-precharge and command interleaving reduce the SDRAM overhead cycles by 70% and increases SDRAM performance by up to 19.2% in the best case. This controller has been implemented in an AVS SoC and the frequency is 200MHz.
文摘This paper describes the method of built-in self-repairing of RAM on board, designs hardware circuit, and logic for the RAM's faults self-repairing system based on FPGA. The key technology is that it utilizes FPGA to test RAM according to some algorithm to find out failure memory units and replace the faulty units with FPGA. Then it can build a memory that has no fault concern to external controller, and realizes the logic binding between external controller and RAM. Micro Controller Unit (MCU) can operate external RAM correctly even if RAM has some fault address units. Conventional MCS-51 is used to simulate the operation of MCU operating external memory. Simulation shows FPGA can complete the faulty address units' mapping and MCU can normally read and write external RAM. This design realizes the RAM's built-in self-repairing on board.
文摘Stateless translation and stateless double translation/encapsulation technologies （IVI/MAP-T/MAP-E） define the address mapping and protocol translation/encapsulation algorithms between IPv4 and IPv6. IVI/MAP-T/MAP-E technologies maintain end-to-end address transparency between IPvd and IPv6 and support communication initiated by IPv4-only or IPv6-only end systems. Therefore, they are the very critical techniques for the IPv4/IPv6 coexistence and transition.
