This paper introduces a high-performance analog front end for a passive UHF RFID transponder IC, which is compatible with the ISO/IEC 18000-6B standard,operating at the 915MHz ISM band with a total supply current cons...This paper introduces a high-performance analog front end for a passive UHF RFID transponder IC, which is compatible with the ISO/IEC 18000-6B standard,operating at the 915MHz ISM band with a total supply current consumption less than 8μA. There are no external components, except for the antenna. The passive IC＇s power supply is taken from the energy of the received RF electromagnetic field with the help of a Schottky diode rectifier. The RFID analog front end includes a local oscillator, clock generator, power on reset circuit, matching network and backscatter,rectifier,regulator, and AM demodulator. The IC, whose reading distance is more than 3m,is fabricated with a Chartered 0.35μm two-poly four-metal CMOS process with Schottky diodes and is EEPROM supported. The core size is 300μm × 720μm.展开更多
Extracting characteristic brain signals and simultaneous recording animals behaving could help us to understand the complex behavior of neuronal ensembles. Here, a system was established to record local field potentia...Extracting characteristic brain signals and simultaneous recording animals behaving could help us to understand the complex behavior of neuronal ensembles. Here, a system was established to record local field potentials (LFP) and extracellular signal or multiple-unit discharge and behavior synchronously by utilizing electrophysiology and integrated circuit technique. It comprised microelectrodes and micro-driver assembly, analog front end (AFE),while a computer (Pentium III ) was used as the platform for the graphic user interface, which was developed using the LabVIEW programming language. It was designed as a part of ongoing research to develop a portable wireless neural signal recording system. We believe that this information will be useful for the research of brain-computer interface.展开更多
This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmab...This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm/℃ bandgap reference and on-chip low-output voltage regulators. A two segment capacitive array structure （6 MSB 5 LSB） composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements. Implemented in the GSMC 0.13 #m 1.5 V/12 V dual-gate 4P6M e-flash process, the analog front end occupies an area of 0.457 mm2 and consumes power of 18.8 mW, in which 1.1 mW cost by the SAR ADC. Measured at 500 kHz input, the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 dB and 60.60 dB respectively, achieving a figure of merit of 350 U/conversion-step.展开更多
A 14-bit,40-MHz analog front end（AFE） for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier（VGA） with nearly 42 dB gain range,a correlat...A 14-bit,40-MHz analog front end（AFE） for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier（VGA） with nearly 42 dB gain range,a correlated double sampler（CDS） with programmable gain functionality,a 14-bit analog-to-digital converter and a programmable timing core.To achieve the maximum dynamic range,the VGA proposed here can linearly amplify the input signal in a gain range from-1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth.A novel CDS takes image information out of noise,and further amplifies the signal accurately in a gain range from 0 to 18 dB in0.035 dB step.A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity.An internal timing core can provide flexible timing for CCD arrays,CDS and ADC.The proposed AFE was fabricated in SMIC 0.18 μm CMOS process.The whole circuit occupied an active area of 2.8×4.8 mm^2 and consumed360 mW.When the frequency of input signal is 6.069 MHz,and the sampling frequency is 40 MHz,the signal to noise and distortion（SNDR） is 70.3 dB,the effective number of bits is 11.39 bit.展开更多
Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems por...Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.展开更多
单对线以太网是近年来新兴的以太网技术,随着汽车自动驾驶和工业物联网的高速发展,凭借上层应用扩展和底层布线上的绝对优势,正在大规模应用。单对线以太网物理层模拟前端技术是实现单对线以太网通信的关键基础技术。本文讲述了现有单...单对线以太网是近年来新兴的以太网技术,随着汽车自动驾驶和工业物联网的高速发展,凭借上层应用扩展和底层布线上的绝对优势,正在大规模应用。单对线以太网物理层模拟前端技术是实现单对线以太网通信的关键基础技术。本文讲述了现有单对线以太网物理层模拟前端相关的标准,架构及相关模块设计技术,重点对发射器TX和接收器RX关键模块的现有实现技术及其优缺点进行了列举分析。发射器TX电流模结构易于实现高精度但功耗效率低,电压模结构精度略低但功耗效率更高;接收器RX的设计围绕模拟数字转换器(Analog-to-Digital Converter,ADC)展开,ADC决定着整个RX的性能、功耗、面积和复杂度,分段和重新装配(Segmentation And Reassembly,SAR)ADC是首选结构,应用上限不断提高。由此进一步明确了在高性能、低功耗、小面积的单对线以太网物理层模拟前端设计中的挑战。展开更多
This paper describes an analog front-end （AFE） intended for portable audio application, which operates at 1 V and consumes only 410 μW. The AFE consists of a 30 dB-gain programmable gain amplifier （PGA） and a 2nd...This paper describes an analog front-end （AFE） intended for portable audio application, which operates at 1 V and consumes only 410 μW. The AFE consists of a 30 dB-gain programmable gain amplifier （PGA） and a 2nd-order 3-bit sigma-delta modulator. The PGA with single input and on-chip common-mode bias voltage shows good noise-reduction performance. The modulator makes use of data weighted averaging to reduce the linearity requirements of the digital-to-analog converter in the feedback loop. The AFE is implemented in the SMIC 0.13μm 1PSM CMOS process. The measurement results show that in a 1 V power supply, at 200 mVp-p, between 100 Hz and 20 kHz, the maximal signal-to-noise ratio is 70 dB, and the total power is 410 μW.展开更多
This paper reports a complimentary metal-oxide-semiconductor （CMOS） analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an ex...This paper reports a complimentary metal-oxide-semiconductor （CMOS） analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I^2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter （∑-△ ADC） are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm^2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L.展开更多
A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimiz...A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 μVrms （0.48-2000 Hz）. The chip is fabricated via a SMIC 0.18μm CMOS process. Although the power consumption is only 32.1 μW under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals.展开更多
文摘This paper introduces a high-performance analog front end for a passive UHF RFID transponder IC, which is compatible with the ISO/IEC 18000-6B standard,operating at the 915MHz ISM band with a total supply current consumption less than 8μA. There are no external components, except for the antenna. The passive IC＇s power supply is taken from the energy of the received RF electromagnetic field with the help of a Schottky diode rectifier. The RFID analog front end includes a local oscillator, clock generator, power on reset circuit, matching network and backscatter,rectifier,regulator, and AM demodulator. The IC, whose reading distance is more than 3m,is fabricated with a Chartered 0.35μm two-poly four-metal CMOS process with Schottky diodes and is EEPROM supported. The core size is 300μm × 720μm.
基金Shandong Science Development FundGrant number:041120101
文摘Extracting characteristic brain signals and simultaneous recording animals behaving could help us to understand the complex behavior of neuronal ensembles. Here, a system was established to record local field potentials (LFP) and extracellular signal or multiple-unit discharge and behavior synchronously by utilizing electrophysiology and integrated circuit technique. It comprised microelectrodes and micro-driver assembly, analog front end (AFE),while a computer (Pentium III ) was used as the platform for the graphic user interface, which was developed using the LabVIEW programming language. It was designed as a part of ongoing research to develop a portable wireless neural signal recording system. We believe that this information will be useful for the research of brain-computer interface.
文摘This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm/℃ bandgap reference and on-chip low-output voltage regulators. A two segment capacitive array structure （6 MSB 5 LSB） composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements. Implemented in the GSMC 0.13 #m 1.5 V/12 V dual-gate 4P6M e-flash process, the analog front end occupies an area of 0.457 mm2 and consumes power of 18.8 mW, in which 1.1 mW cost by the SAR ADC. Measured at 500 kHz input, the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 dB and 60.60 dB respectively, achieving a figure of merit of 350 U/conversion-step.
基金supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033)the National High-Tech Program of China (No. 2013AA014103)the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302)
文摘A 14-bit,40-MHz analog front end（AFE） for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier（VGA） with nearly 42 dB gain range,a correlated double sampler（CDS） with programmable gain functionality,a 14-bit analog-to-digital converter and a programmable timing core.To achieve the maximum dynamic range,the VGA proposed here can linearly amplify the input signal in a gain range from-1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth.A novel CDS takes image information out of noise,and further amplifies the signal accurately in a gain range from 0 to 18 dB in0.035 dB step.A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity.An internal timing core can provide flexible timing for CCD arrays,CDS and ADC.The proposed AFE was fabricated in SMIC 0.18 μm CMOS process.The whole circuit occupied an active area of 2.8×4.8 mm^2 and consumed360 mW.When the frequency of input signal is 6.069 MHz,and the sampling frequency is 40 MHz,the signal to noise and distortion（SNDR） is 70.3 dB,the effective number of bits is 11.39 bit.
文摘Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.
文摘单对线以太网是近年来新兴的以太网技术,随着汽车自动驾驶和工业物联网的高速发展,凭借上层应用扩展和底层布线上的绝对优势,正在大规模应用。单对线以太网物理层模拟前端技术是实现单对线以太网通信的关键基础技术。本文讲述了现有单对线以太网物理层模拟前端相关的标准,架构及相关模块设计技术,重点对发射器TX和接收器RX关键模块的现有实现技术及其优缺点进行了列举分析。发射器TX电流模结构易于实现高精度但功耗效率低,电压模结构精度略低但功耗效率更高;接收器RX的设计围绕模拟数字转换器(Analog-to-Digital Converter,ADC)展开,ADC决定着整个RX的性能、功耗、面积和复杂度,分段和重新装配(Segmentation And Reassembly,SAR)ADC是首选结构,应用上限不断提高。由此进一步明确了在高性能、低功耗、小面积的单对线以太网物理层模拟前端设计中的挑战。
基金Project supported by the National Natural Science Foundation of China(No.61001052)the Beijing Natural Science Foundation(No.4123096)
文摘This paper describes an analog front-end （AFE） intended for portable audio application, which operates at 1 V and consumes only 410 μW. The AFE consists of a 30 dB-gain programmable gain amplifier （PGA） and a 2nd-order 3-bit sigma-delta modulator. The PGA with single input and on-chip common-mode bias voltage shows good noise-reduction performance. The modulator makes use of data weighted averaging to reduce the linearity requirements of the digital-to-analog converter in the feedback loop. The AFE is implemented in the SMIC 0.13μm 1PSM CMOS process. The measurement results show that in a 1 V power supply, at 200 mVp-p, between 100 Hz and 20 kHz, the maximal signal-to-noise ratio is 70 dB, and the total power is 410 μW.
基金Project supported by the National Key Basic Research and Development Project(No.2015CB352103)
文摘This paper reports a complimentary metal-oxide-semiconductor （CMOS） analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I^2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter （∑-△ ADC） are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm^2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L.
基金Project supported by the National High Technology Research and Development Program of China(No.2008AA010702)
文摘A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 μVrms （0.48-2000 Hz）. The chip is fabricated via a SMIC 0.18μm CMOS process. Although the power consumption is only 32.1 μW under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals.
