Metering technology is one of the core technologies of the smart power grid. The overall metering solution and related products have a wide market space in the whole process of power production, which bring new opport...Metering technology is one of the core technologies of the smart power grid. The overall metering solution and related products have a wide market space in the whole process of power production, which bring new opportunities for power distribution development from automation to intelligentialize, and provide technical supports for the power metering system platform. Because of the importance of metering products and their market demand, this paper focuses on the design of a simple power metering chip with low-cost, low-precision and non-invasive, so as to lay the foundation for the development and practical technology accumulation of power metering products. The design achieves low cost by reducing the acquisition accuracy, simplifying the collection and sampling methods. This paper studies the chip accuracy, sampling methods, collection methods, and the inference of the chip characteristics requirements.展开更多
A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test an...A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.展开更多
Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can...Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can be used for NoCs. This paper focuses on the area costs for on-chip routers under four different data-link widths： 8 bits, 16 bits, 128 bits, and 256bits. Firstly, a virtual-channel based on-chip router is introduced. Secondly, the components of the router are implemented by Verilog HDL models and synthesized by Quartus II 4.0 in a FPGA device. Finally, the area costs are analyzed. It can be seen from the results that data-link width has great influence on area costs of buffers and crossbar while has no influence on area costs of arbiter.展开更多
提出了一种新的基于NoC(Network on Chip)的不规则IP模块映射方法。其基本思想是把较大的IP模块分解成几个小的IP虚模型,或把几个较小的IP模块组合成一个IP虚模型,使得每个IP虚模型能映射到NoC结构的一个资源节点上。通过计算曼哈顿距...提出了一种新的基于NoC(Network on Chip)的不规则IP模块映射方法。其基本思想是把较大的IP模块分解成几个小的IP虚模型,或把几个较小的IP模块组合成一个IP虚模型,使得每个IP虚模型能映射到NoC结构的一个资源节点上。通过计算曼哈顿距离和输入/输出度,可以确定每个通信节点中缓冲区的大小。根据计算的通信代价可以对初始映射结果进行调整,从而可以避免通信拥塞,降低系统的功耗。展开更多
文摘Metering technology is one of the core technologies of the smart power grid. The overall metering solution and related products have a wide market space in the whole process of power production, which bring new opportunities for power distribution development from automation to intelligentialize, and provide technical supports for the power metering system platform. Because of the importance of metering products and their market demand, this paper focuses on the design of a simple power metering chip with low-cost, low-precision and non-invasive, so as to lay the foundation for the development and practical technology accumulation of power metering products. The design achieves low cost by reducing the acquisition accuracy, simplifying the collection and sampling methods. This paper studies the chip accuracy, sampling methods, collection methods, and the inference of the chip characteristics requirements.
基金Project supported by the SDC Project of Science and Technology Commission of Shanghai Municipality (Grant No.08706201000)the AM Foundation Project of Science and Technology Commission of Shanghai Municipality (Grant No.08700741000)+1 种基金the Leading Academic Discipline Project of Shanghai Education Commission (Grant No.J50104)the Innovation Foundation Project of Shanghai University
文摘A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.
文摘Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can be used for NoCs. This paper focuses on the area costs for on-chip routers under four different data-link widths： 8 bits, 16 bits, 128 bits, and 256bits. Firstly, a virtual-channel based on-chip router is introduced. Secondly, the components of the router are implemented by Verilog HDL models and synthesized by Quartus II 4.0 in a FPGA device. Finally, the area costs are analyzed. It can be seen from the results that data-link width has great influence on area costs of buffers and crossbar while has no influence on area costs of arbiter.
文摘提出了一种新的基于NoC(Network on Chip)的不规则IP模块映射方法。其基本思想是把较大的IP模块分解成几个小的IP虚模型,或把几个较小的IP模块组合成一个IP虚模型,使得每个IP虚模型能映射到NoC结构的一个资源节点上。通过计算曼哈顿距离和输入/输出度,可以确定每个通信节点中缓冲区的大小。根据计算的通信代价可以对初始映射结果进行调整,从而可以避免通信拥塞,降低系统的功耗。
