A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background

A 14-bit 100-MS/s pipelined analog-to-digital converter（ADC） without dedicated front-end sampleand-hold amplifier（SHA） is presented. In addition to elaborate matching of the sampling network in the first stage,a background offset cancellation circuit is proposed in this paper to suppress the offset of the comparators in the first-stage sub-ADC, which ensures the overall offset does not exceed the correction range of the built-in redundant structure. Fabricated in a 0.18- m CMOS technology, the presented ADC occupies a chip area of 12 mm2, and consumes 237 mW from a 1.8-V power supply. Measurement results with a 30.1-MHz input sine wave under a sampling rate of 100 MS/s show that the ADC achieves a 71-d B signal-to-noise and distortion ratio（SNDR）,an 85.4-d B spurious-free dynamic range（SFDR）, a maximum differential nonlinearity（DNL） of 0.22 LSB and a maximum integral nonlinearity（INL） of 1.4 LSB.

A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS

This paper presents a 0.6 V 10 bit successive approximation register （SAR） ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm^2.