Increasing the Efficiency and Level of Environmental Safety of Pro-Environmental City Heat Supply Technologies by Low Power Nuclear Plants

In connection with the current prospect of decarbonization of coal energy through the use of small nuclear power plants (SNPPs) at existing TPPs as heat sources for heat supply to municipal heating networks, there is a technological need to improve heat supply schemes to increase their environmental friendliness and efficiency. The paper proves the feasibility of using the heat-feeding mode of ASHPs for urban heat supply by heating the network water with steam taken from the turbine. The ratio of electric and thermal power of a “nuclear” combined heat and power plant is given. The advantage of using a heat pump, which provides twice as much electrical power with the same heat output, is established. Taking into account that heat in these modes is supplied with different potential, the energy efficiency was used to compare these options. To increase the heat supply capacity, a scheme with the use of a high-pressure heater in the backpressure mode and with the heating of network water with hot steam was proposed. Heat supply from ASHPs is efficient and environmentally friendly even in the case of significant remoteness of heat consumers.

Soft transmission of 3D video for low power and low complexity scenario

Thanks to the rapid development of naked-eye 3D and wireless communication technology,3D video related applications on mobile devices have attracted a lot of attention.Nevertheless,the time-varying characteristics of the wireless channel is very challenging for conventional source-channel coding based transmission strategy.Also,the high complexity of source-channel coding based transmission scheme is undesired for low power mobile terminals.An advanced transmission scheme named Softcast was proposed to achieve efficient transmission performance for 2D image/video.Unfortunately,it cannot be directly applied to wireless 3D video transmission with high efficiency.This paper proposes a more efficient soft transmission scheme for 3D video with a graceful quality adaptation within a wide range of channel Signal-to-Noise Ratio(SNR).The proposed method first extends the linear transform to 4 dimensions with additional view dimension to eliminate the view redundancy,and then metadata optimization and chunk interleaving are designed to further improve the transmission performance.Meanwhile,a synthesis distortion based chunk discard strategy is developed to improve the overall 3D video quality under the condition of limited bandwidth.The experimental results demonstrate that the proposed method significantly improves the 3D video transmission performance over the wireless channel for low power and low complexity scenarios.

Synthesis Scheme for Low Power Designs Under Timing Constraints

To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The time-constrained algorithm has time complexity of O(n 2),where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46 5%.

Low Power Polarity Conversion Based on the Whole Annealing Genetic Algorithm

For an n-variable logic function,the power dissipation and area of the REED-MULLER （RM） circuit corresponding to each polarity are different. Based on the propagation algorithm of signal probability,the decomposition algorithm of a multi-input XOR/AND gate,and the multiple segment algorithm of polarity conversion,this paper successfully applies the whole annealing genetic algorithm （WAGA） to find the best polarity of an RM circuit. Through testing eight large-scale circuits from the Microelectronics Center North Carolina （MCNC） Benchmark, the SYNOPSYS synthesis results show that the RM circuits corresponding to the best polarity found using the proposed algorithm attain average power,area,and max delay savings of 77.2% ,62.4% ,and 9.2% respectively,compared with those under polarity 0.

Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies

Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed. Eight-input OR gate circuits constructed with these techniques are simulated using 45nm BSIM4 SPICE models in HSPICE. The simulation results show that the proposed circuits effectively lower the active power, reduce the total leakage current, and enhance speed under similar noise immunity conditions. The active power of the two proposed circuits can be reduced by up to 8. 8% and 11.8% while enhancing the speed by 9.5% and 13.7% as compared to dual Vt domino OR gates with no gating stage. At the same time,the total leakage currents are also reduced by up to 80.8% and 82.4% ,respectively. Based on the simulation results,the state of the evaluation node is also discussed to reduce the total leakage currents of dual Vt dominos.

Low Power Design Orienting 384×288 Snapshot Infrared Readout Integrated Circuits

This paper presents a low power design for a 384 x 288 infrared （IR） readout integrated circuit （ROIC）. For the character of IR detector （ ro ≈ 100kΩ, Iint ≈ 100nA）, a novel pixel structure called quad-share buffered direct injection （QSBDI） is proposed and realized. In QSBDI,four neighbor pixels share one buffered amplifier,which creates high injection efficiency, a stable bias, good FPN performance, and low power usage. This ROIC also supports two integration modes （integration then readout and integration while readout）, two selectable gains, and four window readout modes. A test 128 × 128 ROIC is designed,fabricated,and tested. The test results show that the ROIC has good linearity. The peak to peak variance of the sub array is about 10mV. The power of pixel stage is only lmW,and the total power dissipation is 37mW at a working frequency of 4MHz.

Implementation and noise optimization of a 433 MHz low power CMOS LNA

A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.

A 1.45GHz LNA with Low Power,Wide Variable Gain Range and Ultra Low Noise Degradation

A LNA with a novel variable gain solution is presented.Compared with the conventional variable gain solutions of LNA,which have more noise degradations when in low gain mode,this solution gives about 25dB variable gain range in 3dB steps,which would cause ultra low noise figure degradation by 0 3～0 5dB.In addition,extra power consumption is not needed by this solution compared with other solutions.

A Low Voltage,Low Power RF/Analog Front-End Circuit for Passive UHF RFID Tags

This paper presents a low voltage, low power RF/analog front-end circuit for passive ultra high frequency （UHF） radio frequency identification （RFID） tags. Temperature compensation is achieved by a reference generator using sub-threshold techniques. The chip maintains a steady system clock in a temperature range from - 40 to 100℃. Some novel building blocks are developed to save system power consumption,including a zero static current power-on reset circuit and a voltage regulator. The RF/analog front-end circuit is implemented with digital base-band and EEPROM to construct a whole tag chip in 0. 18μm CMOS EEPROM technology without Schottcky diodes. Measured results show that the chip has a minimum supply voltage requirement of 0.75V. At this voltage, the total current consumption of the RF/analog frontend circuit is 4.6μA.

A 0.18μm Transmitter and Receiver with High Speed and Low Power

This paper describes the design of a low voltage differential signal （LVDS） transmitter and receiver with high speed and low power for CPU, LCD, FPGA, and other fast links. In the proposed transmitter, a stable reference and a common mode feedback circuit are integrated into the LVDS drivers, which enable the transmitter to tolerate variations of process, temperature, and supply voltage. The proposed receiver implements a rail-to-rail amplifier architecture that allows a 1.6Gb/s transmission. The transmitter and receiver are implemented in HJ TC 3.3V,0. 18μm CMOS technology. The experimental results demonstrate that the transmitter and receiver reach 1.6Gb/s. The transmitter and receiver pad cells exhibit a power consumption of 35 and 6mW,respectively.

Design of CMOS class-E power amplifier for low power applications

A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.

A Low Power SRAM/SOI Memory Cell Design

A modified four transistor （4T） self-body-bias structured SRAM/SOI memory cell is proposed. The structure is designed and its parameters are obtained by performance simulation and analysis with TSUPREM4 and MEDICI.The structure saves area and its process is simplified by using the body resistor with buried p^＋ channel beneath the nMOS gate instead of the pMOS of 6T CMOS SRAM. Furthermore, this structure can operate safely with a 0.5V supply voltage, which may be prevalent in the near future. Finally, compared to conventional 6T CMOS SRAM,this structure＇s transient responses are normal and its power dissipation is 10 times smaller.

Low power consumption 4-channel variable optical attenuator array based on planar lightwave circuit technique

The power consumption of a variable optical attenuator（VOA） array based on a silica planar lightwave circuit was investigated. The thermal field profile of the device was optimized using the finite-element analysis. The simulation results showed that the power consumption reduces as the depth of the heat-insulating grooves is deeper, the up-cladding is thinner,the down-cladding is thicker, and the width of the cladding ridge is narrower. The materials component and thickness of the electrodes were also optimized to guarantee the driving voltage under 5 V. The power consumption was successfully reduced to as low as 155 mW at an attenuation of 30 dB in the experiment.

Low Power Sensor Design for IoT and Mobile Healthcare Applications

This paper reviews recent advances in radar sensor design for low-power healthcare,indoor real-time positioning and other applications of IoT.Various radar front-end architectures and digital processing methods are proposed to improve the detection performance including detection accuracy,detection range and power consumption.While many of the reported designs were prototypes for concept verification,several integrated radar systems have been demonstrated with reliable measured results with demo systems.A performance comparison of latest radar chip designs has been provided to show their features of different architectures.With great development of IoT,short-range low-power radar sensors for healthcare and indoor positioning applications will attract more and more research interests in the near future.

Low Power Consumption Distributed-Feedback Quantum Cascade Lasers Operating in Continuous-Wave Mode above 90℃ at λ～7.2μm

We report on the design and fabrication of λ-7.2μm distributed feedback quantum cascade lasers lot very high temperature cw operation and low electrical power consumption. The cw operation is reported above 90℃. For a 2-mm-long and 10-μm-wide laser coated with high-reflectivity on the rear facet, more than 170mW of output power is obtained at 20℃ with a threshold power consumption of 2.4 W, corresponding to 30mW with a threshold power consumption of 3.9 W at 90℃. Robust single-mode emission with a side-mode suppression ratio above 25 dB is continuously tunable by the heat sink temperature or injection current.

Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp) sharing is also introduced to decrease the power dissi...

Low power linear actuator for direct drive electrohydraulic valves

This paper presents a bi-directional permanent-magnet linear actuator for directly driving electrohydraulic valves with low power consumption. Its static and dynamic performances were analyzed using the 2D finite element method,taking into account the nonlinear characterization and the eddy current loss of the magnetic material. The experiment and simulation results agree well and show that the prototype actuator can produce a force of ±100 N with the maximum power being 7 W and has linear characteristics with a positive magnetic stiffness within a stroke of ±1 mm. Its non-linearity is less than 1.5% and the hysteresis less than 1.5%. The actuator's frequency response(-3 dB) of the displacement reaches about 15 Hz,and the most significant factor affecting the dynamic performance is identified as the eddy current loss of the magnetic material.

A Novel Ultra Low Power High Performance Atto-Ampere CMOS Current Mirror with Enhanced Bandwidth

A novel CMOS atto-ampere current mirror （AACM） is proposed which reaches the minimum yet reported current range of 0.4 aA. Operation of this circuit is based on the source voltage modulation instead of the conventionally used gate voltage modulation which interestingly prevents usage of commonly required voltage shifting in those circuits. The proposed circuit has a simple structure prohibiting large chip area consumption which consumes extremely low power of 1.5 μW. It is thus the best choice for ultra low power low voltage （ULPLV） applications. By using a very simple frequency compensation technique, its bandwidth is widened to 15.8 kHz. Simulation results in SMIC （Semiconductor Manufacturing International Corporation） 0.18 μm CMOS technology with Hspice are presented to demonstrate the validation of the proposed current mirror.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

Design of a Low Power DSP with Distributed and Early Clock Gating

A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.