Fine-Grain Sleep Transistor Insertion for Leakage Reduction

A fine-grain sleep transistor insertion technique based on our simplified leakage current and delay models is proposed to reduce leakage current. The key idea is to model the leakage current reduction problem as a mixed-integer linear programming （MLP） problem in order to simultaneously place and size the sleep transistors optimally. Because of better circuit slack utilization, our experimental results show that the MLP model can save leakage by 79.75%, 93.56%, and 94.99% when the circuit slowdown is 0%, 3%, and 5%, respectively. The MLP model also achieves on average 74.79% less area penalty compared to the conventional fixed slowdown method when the circuit slowdown is 7%.

FELERION: a new approach for leakage power reduction

The circuit proposed in this paper simultaneously reduces the sub threshold leakage power and saves the state of art aspect of the logic circuits. Sleep transistors and PMOS-only logic are used to further reduce the leakage power. Sleep transistors are used as the keepers to reduce the sub threshold leakage current providing the low resistance path to the output. PMOS-only logic is used between the pull up and pull down devices to mitigate the leakage power further. Our proposed fast efficient leakage reduction circuit not only reduces the leakage current but also reduces the power dissipation. Power and delay are analyzed at the 32 nm BSIM4 model for a chain of four inverters, NAND, NOR and ISCAS-85 c17 benchmark circuits using DSCH3 and the Microwind tool. The simulation results reveal that our proposed approach mitigates leakage power by 90%–94% as compared to the conventional approach.

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory architecture i.e. row and column decoder. In this research work, low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed. In this work, the comparison of cluster DECODER, body bias DECODER, source bias DECODER, and source coupling DE- CODER are designed and analyzed for memory array application. Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool. Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92% and static energy by 99.92% at a supply voltage of 1.2 V. The proposed circuit also improves dynamic power dissipation by 5.69%, dynamic PDP/EDP 65.03% and delay 57.25% at 1.2 V supply voltage.

Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

Multi-threshold complementary metal-oxide- semiconductor （MTCMOS） is ofbn used to reduce the leakage current in idle circuit. Ground bounce noise produced during a transition mode （sleep-to-active） is an important challenge in MTCMOS. In this paper, various noise-aware combinational MTCMOS circuit was used to evaluate the ground bounce noise. An intermediate mode was applied in the sleep-to-active mode transition to reduce the charge stored on virtual lines to real ground. The dependence of ground bounce noise on voltage, transistor size and temperature was investigated with different MTCMOS circuit technique. The peak amplitude of ground bounce noise was reduced up to 78.82%. The leakage current of the circuit was decreased up to 99.73% and the active power of the circuit was reduced up to 62.32%. Simulation of multiplier with different MTCMOS circuit techniques was performed on 45nm CMOS technology.