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基于三电平DPWMA的五电平低共模电压调制及其载波实现
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作者 王付胜 李祯 +3 位作者 付航 郑德佑 姚丹 倪华 《太阳能学报》 EI CAS CSCD 北大核心 2018年第3期749-757,共9页
有源箝位五电平逆变器已逐步运用到大功率光伏并网逆变器中,该文针对其共模电压问题,在三电平断续调制的基础上提出一种五电平低共模电压调制策略。选取五电平空间矢量图中共模电压幅值最小的冗余矢量合成参考矢量,实现全线性工作区... 有源箝位五电平逆变器已逐步运用到大功率光伏并网逆变器中,该文针对其共模电压问题,在三电平断续调制的基础上提出一种五电平低共模电压调制策略。选取五电平空间矢量图中共模电压幅值最小的冗余矢量合成参考矢量,实现全线性工作区内抑制共模电压幅值为直流母线总电压的1/12。根据此矢量思想,提出一种基于零序电压注入的载波实现方法,该方法无需进行复杂的扇区判断和几何运算,易于工程实现。该矢量思想和载波方法极易推广到更多电平的系统中。仿真和实验结果证明调制策略的正确性和可行性。 展开更多
关键词 五电平 断续调制策略 低共模电压 零序电压 载波方法
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LOW-POWER LVDS I/O INTERFACE FOR ABOVE 2GB/S-PER-PIN OPERATION 被引量:3
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作者 Wang Xihu Wu Longsheng Liu Youbao 《Journal of Electronics(China)》 2009年第4期525-531,共7页
Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementat... Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively. 展开更多
关键词 Input/Output (I/O) Low Voltage Differential Signaling (LVDS) TRANSMITTER Receiver Active inductor shunt peaking
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