The performances of analog circuits depend greatly on the layout parasitics and mismatches.Novel techniques are proposed for modeling the distributed parasitic capacitance,parasitic parameter mismatch due to process g...The performances of analog circuits depend greatly on the layout parasitics and mismatches.Novel techniques are proposed for modeling the distributed parasitic capacitance,parasitic parameter mismatch due to process gradient and the inner stack routing mismatch.Based on the proposed models,an optimal stack generation technique is developed to control the parasitics and mismatches,optimize the stack shape and ensure the generation of an Eulerian graph for a given CMOS analog module.An OPA circuit example is given to demonstrate that the circuit performances such as unit gain bandwidth and phase margin are enhanced by the proposed layout optimization method.展开更多
This paper introduces a novel automatic physical synthesis methodology for analog circuits based on the signal-flow analysis.Circuit analysis sub-system adopts the newly advanced methodology,circuit topology analysis,...This paper introduces a novel automatic physical synthesis methodology for analog circuits based on the signal-flow analysis.Circuit analysis sub-system adopts the newly advanced methodology,circuit topology analysis,and circuit sensitivity analysis to generate layout constraints and control performance degradations.Considering the heuristic information about signal-flow,complexity of the methodology is less than the pure performance-driven methodology.And then these constraints are implemented in device generation,placement,and routing sub-systems separately,which makes the different constraints be satisfied at most easily implemented stages.Excellent circuit performance obtained by the methodology is demonstrated by practical circuit examples.展开更多
文摘The performances of analog circuits depend greatly on the layout parasitics and mismatches.Novel techniques are proposed for modeling the distributed parasitic capacitance,parasitic parameter mismatch due to process gradient and the inner stack routing mismatch.Based on the proposed models,an optimal stack generation technique is developed to control the parasitics and mismatches,optimize the stack shape and ensure the generation of an Eulerian graph for a given CMOS analog module.An OPA circuit example is given to demonstrate that the circuit performances such as unit gain bandwidth and phase margin are enhanced by the proposed layout optimization method.
文摘This paper introduces a novel automatic physical synthesis methodology for analog circuits based on the signal-flow analysis.Circuit analysis sub-system adopts the newly advanced methodology,circuit topology analysis,and circuit sensitivity analysis to generate layout constraints and control performance degradations.Considering the heuristic information about signal-flow,complexity of the methodology is less than the pure performance-driven methodology.And then these constraints are implemented in device generation,placement,and routing sub-systems separately,which makes the different constraints be satisfied at most easily implemented stages.Excellent circuit performance obtained by the methodology is demonstrated by practical circuit examples.
