On the basis of mutual compensation of mobility and threshold voltage temperature effects, a stable CMOS band-gap voltage reference circuit was designed and fabricated in CSMC-HJ 0.6 μm CMOS technology. Operating fro...On the basis of mutual compensation of mobility and threshold voltage temperature effects, a stable CMOS band-gap voltage reference circuit was designed and fabricated in CSMC-HJ 0.6 μm CMOS technology. Operating from 0 to 85 ℃ under a supply voltage ranging from 4.5 to 5.5 V, the voltage reference circuit offers an output reference voltage ranging from 1.122 to 1.176 V and a voltage variation less than ±3.70%. The chip size including bonding pads is only 0.4 mm×0.4 mm and the power dissipation falls inside the scope of 28.3 to 48.8 mW operating at a supply voltage of 4.5 to 5.5 V.展开更多
New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study o...New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.展开更多
Carbon nanotubes （CNTs） have emerged as an important material for printed macroelectronics. However, achieving printed complementary macroelectronics solely based on CNTs is difficult because it is still challenging...Carbon nanotubes （CNTs） have emerged as an important material for printed macroelectronics. However, achieving printed complementary macroelectronics solely based on CNTs is difficult because it is still challenging to make reliable n-type CNT transistors. In this study, we report threshold voltage （Vth） tuning and printing of complementary transistors and inverters composed of thin films of CNTs and indium zinc oxide （IZO） as p-type and n-type transistors, respectively. We have optimized the Vth of p-type transistors by comparing Ti/Au and Ti/Pd as source/drain electrodes, and observed that CNT transistors with Ti/Au electrodes exhibited enhancement mode operation （Vth 〈 0）. In addition, the optimized In：Zn ratio offers good n-type transistors with high on-state current （Ion） and enhancement mode operation （Vth 〉 0）. For example, an In：Zn ratio of 2：1 yielded an enhancement mode n-type transistor with Vth - 1 V and Ion of 5.2 μA. Furthermore, by printing a CNT thin film and an IZO thin film on the same substrate, we have fabricated a complementary inverter with an output swing of 99.6% of the supply voltage and a voltage gain of 16.9. This work shows the promise of the hybrid integration of p-type CNT and n-type IZO for complementary transistors and circuits.展开更多
文摘On the basis of mutual compensation of mobility and threshold voltage temperature effects, a stable CMOS band-gap voltage reference circuit was designed and fabricated in CSMC-HJ 0.6 μm CMOS technology. Operating from 0 to 85 ℃ under a supply voltage ranging from 4.5 to 5.5 V, the voltage reference circuit offers an output reference voltage ranging from 1.122 to 1.176 V and a voltage variation less than ±3.70%. The chip size including bonding pads is only 0.4 mm×0.4 mm and the power dissipation falls inside the scope of 28.3 to 48.8 mW operating at a supply voltage of 4.5 to 5.5 V.
文摘New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.
文摘Carbon nanotubes （CNTs） have emerged as an important material for printed macroelectronics. However, achieving printed complementary macroelectronics solely based on CNTs is difficult because it is still challenging to make reliable n-type CNT transistors. In this study, we report threshold voltage （Vth） tuning and printing of complementary transistors and inverters composed of thin films of CNTs and indium zinc oxide （IZO） as p-type and n-type transistors, respectively. We have optimized the Vth of p-type transistors by comparing Ti/Au and Ti/Pd as source/drain electrodes, and observed that CNT transistors with Ti/Au electrodes exhibited enhancement mode operation （Vth 〈 0）. In addition, the optimized In：Zn ratio offers good n-type transistors with high on-state current （Ion） and enhancement mode operation （Vth 〉 0）. For example, an In：Zn ratio of 2：1 yielded an enhancement mode n-type transistor with Vth - 1 V and Ion of 5.2 μA. Furthermore, by printing a CNT thin film and an IZO thin film on the same substrate, we have fabricated a complementary inverter with an output swing of 99.6% of the supply voltage and a voltage gain of 16.9. This work shows the promise of the hybrid integration of p-type CNT and n-type IZO for complementary transistors and circuits.
