In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles...In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles of FPGA verification are introduced.Then,the structure of the FPGA board and the verification methods are illustrated.Finally,the workflow of FPGA verification for audio video coding standard(AVS)decoder and the method of restoring images are introduced in detail.The FPGA resources occupancy is shown and analyzed.The result shows that FPGA can verify the ASIC rapidly and effectively so as to shorten the development cycle.展开更多
We present a new normal basis multiplication scheme using a multiplexer-based algorithm. In this algorithm, the proposed multiplier processes in parallel and has a multiplexer-based structure that uses MUX and XOR gat...We present a new normal basis multiplication scheme using a multiplexer-based algorithm. In this algorithm, the proposed multiplier processes in parallel and has a multiplexer-based structure that uses MUX and XOR gates instead of AND and XOR gates. We show that our multiplier for type-1 and type-2 normal bases saves about 8% and 16%, respectively, in space complexity as compared to existing normal basis multipliers. Finally, the proposed architecture has regular and modular con-figurations and is well suited to VLSI implementations.展开更多
基金Science and Technology Key Project of Guangzhou(2007Z3-D3101)Production and Research Project of Zhuhai(PC20082002)Technology Innovation Project of Guangdong Province(2008778113)
文摘In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles of FPGA verification are introduced.Then,the structure of the FPGA board and the verification methods are illustrated.Finally,the workflow of FPGA verification for audio video coding standard(AVS)decoder and the method of restoring images are introduced in detail.The FPGA resources occupancy is shown and analyzed.The result shows that FPGA can verify the ASIC rapidly and effectively so as to shorten the development cycle.
文摘We present a new normal basis multiplication scheme using a multiplexer-based algorithm. In this algorithm, the proposed multiplier processes in parallel and has a multiplexer-based structure that uses MUX and XOR gates instead of AND and XOR gates. We show that our multiplier for type-1 and type-2 normal bases saves about 8% and 16%, respectively, in space complexity as compared to existing normal basis multipliers. Finally, the proposed architecture has regular and modular con-figurations and is well suited to VLSI implementations.
