A Single-Board Integrated Millimeter-Wave Asymmetric Full-Digital Beamforming Array for B5G/6G Applications

In this article,a single-board integrated millimeter-wave(mm-Wave)asymmetric full-digital beamforming(AFDBF)array is developed for beyond-fifth-generation(B5G)and sixth-generation(6G)communications.The proposed integrated array effectively addresses the challenge of arranging a large number of ports in a full-digital array by designing vertical connections in a three-dimensional space and successfully integrating full-digital transmitting(Tx)and receiving(Rx)arrays independently in a single board.Unlike the traditional symmetric array,the proposed asymmetric array is composed of an 8×8 Tx array arranged in a square shape and an 8+8 Rx array arranged in an L shape.The center-to-center distance between two adjacent elements is 0.54k0 for both the Tx and Rx arrays,where k0 is the free-space wavelength at 27 GHz.The proposed AFDBF array possesses a more compact structure and lower system hardware cost and power consumption compared with conventional brick-type full-digital arrays.In addition,the energy efficiency of the proposed AFDBF array outperforms that of a hybrid beamforming array.The measurement results indicate that the operating frequency band of the proposed array is 24.25–29.50 GHz.An eight-element linear array within the Tx array can achieve a scanning angle ranging from-47°to+47°in both the azimuth and the elevation planes,and the measured scanning range of each eight-element Rx array is–45°to+45°.The measured maximum effective isotropic radiated power(EIRP)of the eight-element Tx array is 43.2 dBm at 28.0 GHz(considering the saturation point).Furthermore,the measured error vector magnitude(EVM)is less than 3%when 64-quadrature amplitude modulation(QAM)waveforms are used.

Full-digital real-time power system simulator conferred nation's top award

On January 11, 2010, the grand ceremony to present the 2009 National Scientific and Technological Award was held in Beijing. The project—Development and Implementation of Full-Digital Real-Time

SFD-AGC algorithm with ADC digitalizing bit fully utilized and stable PAR

Aiming at making full use of analog to digital converter （ADC） digitalizing bit without oversaturation while keeping peak to average ratio （PAR） stable, this paper puts forward a new segmented full-digital （SFD）-automatic gain control （AGC） algorithm for a new long term evolution （LTE） communication system. Segmented digital gain control strategy is adopted to adjust the gain by only one step based on detected power status. Whether the gain needs to be adjusted is determined by current signal state derived from the change ranges of adjacent root mean square （RMS） of input signal, but not the difference between the power level of current signal and target signal. Software simulation and hardware implementing had been conducted with LTE frequency division dual （FDD） uplink signal and the results indicated that the proposed AGC algorithm can judge power status accurately and hence adjust the gain precisely in one step with a short delay, further, it can make full use of ADC digitalizing bit without oversaturation as well as keeping stable PAR. In addition, the mean error vector magnitude （EVM） was confined less than 1.6% to meet the 3rd generation partnership project （3GPP） standard well.

Fast corrector power supply design for HEPS

Background High-energy photon source under construction is a fourth-generation synchrotronradiation light source with energy of 6 Gev and ultra-low emittance(lower than 0.1 nm rad).The ultra-low beam emittance requires high beam stability.Purpose In order to meet this requirement of low beam emittance,the fast close orbit correctionsystem is used to keep beam on the right orbit.The fast close orbit correction system need fast corrector power supply to drive the calibration magnet to complete track correction.So,a fastcorrector power supply prototype with high bandwidth and low current ripple to improve the performance of the fast close orbit correction system to prove the high beam stability had beendeveloped.Methods The prototype use a novel multilevel switch-mode structure to provide the dynamicrequirement.The prototype adopts FPGA for full-digital control and use high-speed ADC with temperature control.By using a precision sampling circuit(ADC+DCCT),the prototypeoutputs current ripple can meet the requirement.Results and conclusion The designed for HEPS meet the design requirement.Through test,the prototype has asmall signal bandwidth of 10 kHz and output current ripple lower than 20 ppm.

A precision ADC sampling system design

Introduction The high-energy photon source,which has been built in Huairou,Beijing,has high requirements on magnetic field dithering.Magnetic field dithering is mainly determined by the stability of the output current of the power supply.In order to ensure the stability of the output current of quadrupole magnet power supply,the power supply sampling control loop needs to be precisely designed.In this paper,a precision ADC sampling system based on internal temperature control is designed to carry out precise control of the sampling ADC.Materials In this design,precise ADC chip is used to complete the precise sampling of the system.The precise sampling system contains a DAC system for high-speed settings.Methods In order to verify the design of the system,high-precision quadrupolemagnet power supply is used for measurement.Conclusion The experimental results show that the temperature variation range of precision temperature control ADC system is±0.1°C.By using the precise temperature controlADCsystem,the output current stability of the high-precision quadrupole magnet power supply is effectively improved.