Low-Power Design of Ethernet Data Transmission

For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array （FPGA）, a low-power consumption design method is proposed, which is suitable for FPGA implementation. To reduce the dynamic power consumption of integrated circuit （IC） design, the proposed method adopts the dynamic control of the clock frequency. For most of the time, when the port is in the idle state or lower-rate state, users can reduce or even turn off the reading clock frequency and reduce the clock flip frequency in order to reduce the dynamic power consumption. When the receiving rate is high, the reading clock frequency will be improved timely to ensure that no data will lost. Simulated and verified by Modelsim, the proposed method can dynamically control the clock frequency, including the dynamic switching of high-speed and low-speed clock flip rates, or stop of the clock flip.

Design of Low-Power Data Logger of Deep Sea for Long-Term Field Observation

This paper describes the implementation of a data logger for the real-time in-situ monitoring of hydrothermal systems. A compact mechanical structure ensures the security and reliability of data logger when used under deep sea. The data logger is a battery powered instrument, which can connect chemical sensors （pH electrode, H2S electrode, H2 electrode） and temperature sensors. In order to achieve major energy savings, dynamic power management is implemented in hardware design and software design. The working current of the data logger in idle mode and active mode is 15 μA and 1.44 mA respectively, which greatly extends the working time of battery. The data logger has been successftdly tested in the first Sino-American Cooperative Deep Submergence Project from August 13 to September 3, 2005.

On-Chip Micro Temperature Controllers Based on Freestanding Thermoelectric Nano Films for Low-Power Electronics

Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity of temperature distribution in microsystems,making precise temperature control for electronic components extremely challenging.Herein,we report an on-chip micro temperature controller including a pair of thermoelectric legs with a total area of 50×50μm^(2),which are fabricated from dense and flat freestanding Bi2Te3-based ther-moelectric nano films deposited on a newly developed nano graphene oxide membrane substrate.Its tunable equivalent thermal resistance is controlled by electrical currents to achieve energy-efficient temperature control for low-power electronics.A large cooling temperature difference of 44.5 K at 380 K is achieved with a power consumption of only 445μW,resulting in an ultrahigh temperature control capability over 100 K mW^(-1).Moreover,an ultra-fast cooling rate exceeding 2000 K s^(-1) and excellent reliability of up to 1 million cycles are observed.Our proposed on-chip temperature controller is expected to enable further miniaturization and multifunctional integration on a single chip for microelectronics.

Low-power system model for quantum entangled photon-pair source

The quantum entangled photon-pair source,as an essential component of optical quantum systems,holds great potential for applications such as quantum teleportation,quan-tum computing,and quantum imaging.The current workhorse technique for preparing photon pairs involves performing spon-taneous parametric down conversion(SPDC)in bulk nonlinear crystals.However,the current power consumption and cost of preparing entangled photon-pair sources are relatively high,pos-ing challenges to their integration and scalability.In this paper,we propose a low-power system model for the quantum entan-gled photon-pair source based on SPDC theory and phase matching technology.This model allows us to analyze the per-formance of each module and the influence of component cha-racteristics on the overall system.In our experimental setup,we utilize a 5 mW laser diode and a typical type-II barium metabo-rate(BBO)crystal to prepare an entangled photon-pair source.The experimental results are in excellent agreement with the model,indicating a significant step towards achieving the goal of low-power and low-cost entangled photon-pair sources.This achievement not only contributes to the practical application of quantum entanglement lighting,but also paves the way for the widespread adoption of optical quantum systems in the future.

New design solutions for low-power energy production in water pipe systems

This study is the result of ongoing research for a European Union 7th Framework Program Project regarding energy converters for very low heads, and aims to analyze optimization of new cost-effective hydraulic turbine designs for possible implementation in water supply systems （WSSs） or in other pressurized water pipe infrastructures, such as irrigation, wastewater, or drainage systems. A new methodology is presented based on a theoretical, technical and economic analysis. Viability studies focused on small power values for different pipe systems were investigated. Detailed analyses of alternative typical volumetric energy converters were conducted on the basis of mathematical and physical fundamentals as well as computational fluid dynamics （CFD） associated with the interaction between the flow conditions and the system operation. Important constraints （e.g., size, stability, efficiency, and continuous steady flow conditions） can be identified and a search for alternative rotary yolumetric converters is being conducted. As promising cost-effective solutions for the coming years, adapted rotor-dynamic turbomachines and non-conventional axial propeller devices were analyzed based on the basic principles of pumps operating as turbines, as well as through an extensive comparison between simulations and experimental tests.

Low-power emerging memristive designs towards secure hardware systems for applications in internet of things

Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security applications in the era of internet of things(IoT).In this review article,for achieving secure hardware systems in IoT,lowpower design techniques based on emerging memristive technology for hardware security primitives/systems are presented.By reviewing the state-of-the-art in three highlighted memristive application areas,i.e.memristive non-volatile memory,memristive reconfigurable logic computing and memristive artificial intelligent computing,their application-level impacts on the novel implementations of secret key generation,crypto functions and machine learning attacks are explored,respectively.For the low-power security applications in IoT,it is essential to understand how to best realize cryptographic circuitry using memristive circuitries,and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security.This review article aims to help researchers to explore security solutions,to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs.

Ethernet Controller SoC Design and Its Low-Power DFT Considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.

Novel Design of Low-power Multiplex Differential Voltage Comparators

A novel design of multiplex differential voltage comparators(MDVC) is presented for reducing current and power dissipation. According to the special properties of relational operation and logical operation, parts of the comparators are redundant in some instances, and thus can be turned off. By selecting and switching the current routes, several effective differential pairs are biased by a single tail current stage-by-stage and the redundant comparators are turned off by cutting their tail currents. As a result, the quiescent current and power consumption are greatly decreased. The switching of current is achieved by the input differential pair transistors themselves and hence no extra switches are required. When a MDVC is used in a flash analog-to-digital converter(ADC), its current dissipation is much lower than that of the conventional comparators. This architecture can also be used in window-comparators, maximum or minimum comparators, and comparators for logical operations. The power dissipation in all these cases could be reduced significantly.

Design of low-offset low-power CMOS amplifier for biosensor application

A compacted and low-offset low-power CMOS am- plifier for biosensor application is presented in this paper. It includes a low offset Op-Amp and a high precision current reference. With a novel continuous-time DC offset rejection scheme, the IC achieves lower offset voltage and lower power consumption compared to previous designs. This configuration rejects large DC offset and drift that exist at the skin-electrode interface without the need of external components. The proposed amplifier has been implemented in SMIC 0.18-μm 1P6M CMOS technol-ogy, with an active silicon area of 100 μm by 120 μm. The back-annotated simulation results demonstrated the circuit features the systematic offset voltage less than 80 μV, the offset drift about 0.27 μV/℃ for temperature ranging from –30℃ to 100℃ and the total power dissipation consumed as low as 37.8 μW from a 1.8 V single supply. It dedicated to monitor low amplitude biomedical signals recording.

Predictor−corrector inverse design scheme for property−composition prediction of amorphous alloys

In order to develop a generic framework capable of designing novel amorphous alloys with selected target properties,a predictor−corrector inverse design scheme(PCIDS)consisting of a predictor module and a corrector module was presented.A high-precision forward prediction model based on deep neural networks was developed to implement these two parts.Of utmost importance,domain knowledge-guided inverse design networks(DKIDNs)and regular inverse design networks(RIDNs)were also developed.The forward prediction model possesses a coefficient of determination(R^(2))of 0.990 for the shear modulus and 0.986 for the bulk modulus on the testing set.Furthermore,the DKIDNs model exhibits superior performance compared to the RIDNs model.It is finally demonstrated that PCIDS can efficiently predict amorphous alloy compositions with the required target properties.

Design Strategies Applied to Classroom's Daylight Design Optimization of Classrooms Design

This paper explains how the optimized classrooms were selected and the results that were achieved by the optimizations carried out and finalized.The context of the research is the city of Concepción,in Chile.Virtual models of classrooms were evaluated using the Radiance software.We used a methodology that allowed us to determine the luminous conditions under different types of skies,seasons of the year and times of the day.The evaluation of the typologies was performed based on three defined criteria,in order to achieve the stated design objectives.We defined the optimal solutions for each orientation and,finally,we stated design recommendations for daylit classrooms to ensure the visual comfort of the students.These recommendations link all that found in the initial analysis with that found in the optimization stage.

Design of a Low-Power CMOS LVDS I/O Interface Circuit

The paper presents the design and implementation of LVDS （low-voltage differential signaling） receiver circuit, fully compatible with LVDS standard. The proposed circuit is composed of the telescopic amplifier and the comparator with internal hysteresis. The receiver supports 3.5 Gbps data rate with 7.4 mA current at 1.8 V supply according to post-layout circuit simulations. The circuit has the power consumption of 13.1 MW. Comparing with the conventional circuit, the circuit is achieved to reduce the power consumption by 19.1% and the data rate by 14.3 %. The validity and effectiveness of the proposed circuit are verified through the circuit simulation with Samsung 0.18 μm CMOS （complementary metal-oxide-semiconductor） standard technology under the 1.8 V supply voltage.

Low-Power Digital Circuit Design with Triple-Threshold Voltage

Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

Design strategies and insights of flexible infrared optoelectronic sensors

Infrared optoelectronic sensing is the core of many critical applications such as night vision,health and medication,military,space exploration,etc.Further including mechanical flexibility as a new dimension enables novel features of adaptability and conformability,promising for developing next-generation optoelectronic sensory applications toward reduced size,weight,price,power consumption,and enhanced performance(SWaP^(3)).However,in this emerging research frontier,challenges persist in simultaneously achieving high infrared response and good mechanical deformability in devices and integrated systems.Therefore,we perform a comprehensive review of the design strategies and insights of flexible infrared optoelectronic sensors,including the fundamentals of infrared photodetectors,selection of materials and device architectures,fabrication techniques and design strategies,and the discussion of architectural and functional integration towards applications in wearable optoelectronics and advanced image sensing.Finally,this article offers insights into future directions to practically realize the ultra-high performance and smart sensors enabled by infrared-sensitive materials,covering challenges in materials development and device micro-/nanofabrication.Benchmarks for scaling these techniques across fabrication,performance,and integration are presented,alongside perspectives on potential applications in medication and health,biomimetic vision,and neuromorphic sensory systems,etc.

Biomechanical Study of Different Scaffold Designs for Reconstructing a Traumatic Distal Femur Defect Using Patient-Specific Computational Modeling

Reconstruction of a traumatic distal femur defect remains a therapeutic challenge.Bone defect implants have been proposed to substitute the bone defect,and their biomechanical performances can be analyzed via a numerical approach.However,the material assumptions for past computational human femur simulations were mainly homogeneous.Thus,this study aimed to design and analyze scaffolds for reconstructing the distal femur defect using a patient-specific finite element modeling technique.A three-dimensional finite element model of the human femur with accurate geometry and material distribution was developed using the finite element method and material mapping technique.An intact femur and a distal femur defect model treated with nine microstructure scaffolds and two solid scaffolds were investigated and compared under a single-leg stance loading.The results showed that the metal solid scaffold design could provide the most stable fixation for reconstructing the distal femur defect.However,the fixation stability was affected by various microstructure designs and pillar diameters.A microstructure scaffold can be designed to satisfy all the biomechanical indexes,opening up future possibilities for more stable reconstructions.A three-dimensional finite element model of the femur with real bone geometry and bone material distribution can be developed,and this patient-specific femur model can be used for studying other femoral fractures or injuries,paving the way for more comprehensive research in the field.Besides,this patient-specific finite element modeling technique can also be applied to developing other human or animal bone models,expanding the scope of biomechanical research.

Seismic isolation design and resilience improvement of railway station considering the influence of near-fault pulse-like ground motions

To improve the resilience of railway stations,a typical station was selected as the research object,and an isolation design was introduced.Twenty-four groups of near-fault pulse-like ground motions were selected.The seismic resilience of the no-isolation railway stations(NIRS)and the isolation railway stations(IRS)were compared to provide a numerical result of the improvement in resilience.The results show that in the station isolation design,the station's functional requirements and structural characteristics should be considered and the appropriate placement of isolation bearings is under the waiting room.Under the action of a rare earthquake,the repair cost,repair time,rate of harm and death of the IRS were decreased by 8.04 million,18.30 days,6.93×10^(-3)and 1.21×10^(-3),respectively,when compared to the NIRS.The IRS received a seismic resilience grade of three-stars and the NIRS only one-star,indicating that rational isolation design improves the seismic resilience of stations.Thus,for the design of stations close to earthquake faults,it is suggested to utilize appropriate isolation techniques to improve their seismic resilience.

Parametric Analysis and Designing Maps for Powder Spreading in Metal Additive Manufacturing

Powder bed fusion(PBF)in metallic additive manufacturing offers the ability to produce intricate geometries,high-strength components,and reliable products.However,powder processing before energy-based binding significantly impacts the final product’s integrity.Processing maps guide efficient process design to minimize defects,but creating them through experimentation alone is challenging due to the wide range of parameters,necessitating a comprehensive computational parametric analysis.In this study,we used the discrete element method to parametrically analyze the powder processing design space in PBF of stainless steel 316L powders.Uniform lattice parameter sweeps are often used for parametric analysis,but are computationally intensive.We find that non-uniform parameter sweep based on the low discrepancy sequence(LDS)algorithm is ten times more efficient at exploring the design space while accurately capturing the relationship between powder flow dynamics and bed packing density.We introduce a multi-layer perceptron(MLP)model to interpolate parametric causalities within the LDS parameter space.With over 99%accuracy,it effectively captures these causalities while requiring fewer simulations.Finally,we generate processing design maps for machine setups and powder selections for efficient process design.We find that recoating speed has the highest impact on powder processing quality,followed by recoating layer thickness,particle size,and inter-particle friction.

A Low-Power-Consumption 9bit 10MS/s Pipeline ADC for CMOS Image Sensors

A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.

基于Altium Designer软件的电子控制技术中电路设计探究

在正常的电路设计方案中,需要软硬件的互相搭配使用,普通的电路运用收稿方式或简单的办公辅助软件来完成绘制,但在面对复杂情况下的电路,专业的EDA辅助设计软件作用可以显而易见,以该辅助软件设计如SCH(电路原理图)与PCB(印制电路板)文件方面的工作。电子控制技术中电路随着时代的进步而不断创新,新型器件的不断迭代更新,其中的电路设计也变得复杂且繁琐,传统的电路设计已无法胜任最新电路的完善和使用。此时运用AD16(Altium Designer)这款辅助设计软件进行电路设计就可以事半功倍,AD都是复杂电路设计中的高效工具。

水田动力底盘逆向建模与质心验证——基于Geomagic Design X

针对目前农业机械仿真和优化模型精度不高的问题,提出了一种构建精确模型的逆向建模方法。应用光学扫描仪采集点云数据,基于Geomagic Design X处理点云数据并重构零部件模型,在SolidWorks中完成水田动力底盘的装配。以VP6D-CQ型水田动力底盘为例,将测得的实际质心位置与所建的模型质心位置进行比较,并对提出的逆向建模方法进行了试验验证以及误差分析。结果表明:总质量、x坐标、y坐标、z坐标的误差值分别为4.55%、3.62%、2.23%、4.81%,误差值均在5%内。此方法可构建准确的三维模型,为后续仿真优化数据精确性奠定了基础,与传统的研发相比较,可缩短农业机械研发周期、降低设计成本。