基于新型环形放大器的低功耗Pipelined SAR ADC

针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。

List-Serial Pipelined Hardware Architecture for SCL Decoding of Polar Codes

For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.

基于Pipelined结构的电流型CMOS模数转换器电路设计

低功耗设计在当前超大规模集成电路中越来越重要.以电流信号为转换对象,利用电流传输理论,结合电流型CMOS电路设计技术,设计了8位基于Pipelined结构的ADC电路.结果表明,利用电流型CMOS电路可方便地实现电流信号的加减与放大运算,避免了使用传统Pipelined电路结构中的运算放大器电路,因此电路结构简单,可显著降低电路的功耗,提高转换速度,计算机仿真结果表明,电路功能正确.

PIPELINED多值A/D转换器

通过对多值ADC数学表示的分析，指出了多值ADC具有更高的信息密度。本文结合数字电路的开关信号理论，设计了Pipelined三值ADC。该ADC在保证较高转换速度的同时具有相对简单的电路结构。

An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.

1.5位pipelined ADC单级传函的数模分析

1.5位结构是构成pipelined ADC的基本单元,总结了2位向1.5位方案传函的演变过程,但对转换的最优性并未证明。在此通过理论分析揭示了ADC及其单级传输函数变换的本质,证明了在Pipeline结构中,ADC单级传输函数演变的本质是:通过单级传函的变化,使整个ADC最终的传输函数与我们所习惯使用的(或者说最初使用的),相差不大于1个LSB,同时在参考电压失调,子DAC输出失调或者增益错误方面获得一定的鲁棒性。

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Optimization of Power Dissipation in Pipelined Analog-to-Digital Converter

Power optimization for pipelined analog-to-digital converter(ADC) was studied. Operational principle of pipelined ADC was discussed and noise voltage caused by two important thermal noise sources, sampling switch and amplifier,was quantitatively analyzed. Method used to minimize power and the values under simple model were presented. Power can be saved by making the sampling and feedback capacitors scale down in the pipeline.And the size of capacitors was limited by thermal noise in high resolution ADC.The equivalent circuits of the two important thermal noise sources were established.Thermal noise was optimally distributed among the pipeline stages,and the relationship between scaling factor and closed loop gain was obtained for minimum power dissipation.Typical closed loop gain was 2 or 4 in pipeline ADC, and the corresponding scaling factor was (1.217) and 1.317.These results can serve as useful guidelines for designers to minimize the ADC′s power consumption.

A FAST FOREGROUND DIGITAL CALIBRATION TECHNIQUE FOR PIPELINED ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.

Design of Pipelined ADC Using Op Amp Sharing Technique

This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.

DESIGN AND EVALUATION OF A PIPELINED FORWARDING ENGINE

Recent advances in broadband technology have caused forwarding engines to handle pack- ets with over 10 gigabit per second. In this paper, we present a high-speed forwarding pipeline which can finish all of the routing and forwarding tasks in the way of pipelining. We also establish the analysis model of the pipeline with which one can evaluate some key performance parameters of the forwarding engine such as forwarding rate and forwarding delay. We find that the pipeline is of good scalability and can forward unicast packets up to the speed of 40Gbit/s.

Deeply pipelined interpolation architecture for full ultra-HD H.265/HEVC video encoding

Fractional motion estimation(FME) improves the video encoding efficiency significantly. However, its high computational complexity limits the real-time processing capability. Therefore, it is a key problem to reduce the implementation complexity of FME, especially in hardware design. This paper presents a novel deeply pipelined interpolation architecture of FME for the real-time realization of H.265/HEVC full Ultra-HD video encoder. First, a pipelined interpolation architecture together with an elegant processing order is proposed to deal with different search positions in parallel without pipeline stall and data conflict. Second, interpolation results sharing strategies are exploited among search positions to reduce the memory cost. Finally, the structure of the interpolation filter is further optimized for an area efficient implementation. As a result, the proposed design costs 41 917 slice LUTs on the Xilinx Kintex-7 FPGA platform with a 308 MHz working frequency. The measured throughput reaches a record of 1.238 Gpixels/s, which is sufficient for the real-time encoding of 8192×4320@ 30 fps video.

Efficient pipelined flow classification for intelligent data processing in IoT

The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things(IoT).In recent years,researchers have tried to develop hardware-based solutions for the classification of Internet packets.Due to higher throughput and shorter delays,these solutions are considered as a major key to improving the quality of services.Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput.The proposed architectures,however,cannot reach a compromise among power consumption,memory usage,and throughput rate.In view of this,the architecture proposed in this paper contains a pipelinebased micro-core that is used in network processors to classify packets.To this end,three architectures have been implemented using the proposed micro-core.The first architecture performs parallel classification based on header fields.The second one classifies packets in a serial manner.The last architecture is the pipeline-based classifier,which can increase performance by nine times.The proposed architectures have been implemented on an FPGA chip.The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput.The architecture has a power consumption of is 1.294w,and its throughput with a frequency of 233 MHz exceeds 147 Gbps.

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

An integrated MINLP model for multi-party coordination in downstream oil supply chain

Cooperation among enterprises can bring overall and individual performance improvement,and a smooth coordination method is indispensable.However,due to the lack of customized coordination methods,cooperation in the downstream oil supply chain cannot be carried out smoothly.This paper intends to propose a multi-party coordination method to promote cooperation between oil shippers and pipeline operator by optimizing oil transportation,oil substitution and pipeline pricing schemes.An integrated game-theoretic modeling and analysis approach is developed to characterize the operation behaviors of all stakeholders in the downstream oil supply chain.The proposed mixed integer nonlinear programming model constrains supply and demand capacity,transportation routes,oil substitution rules and pipeline freight levels.Logarithm transformation and price discretization are introduced for model linear approximation.Simulation experiments are carried out in the oil distribution system in South China.The results show that compared to the business-as-usual scheme,the new scheme saves transportation cost by 3.48%,increases pipeline turnover by 5.7%,and reduces energy consumption and emissions by 7.66%and 6.77%.It is proved that the proposed method improves the revenue of the whole system,achieves fair revenue distribution,and also improves the energy and environmental benefits of the oil supply chain.

Pipeline thickness estimation using the dispersion of higher-order SH guided waves

Thickness measurement plays an important role in the monitoring of pipeline corrosion damage. However, the requirement for prior knowledge of the shear wave velocity in the pipeline material for popular ultrasonic thickness measurement limits its widespread application. This paper proposes a method that utilizes cylindrical shear horizontal(SH) guided waves to estimate pipeline thickness without prior knowledge of shear wave velocity. The inversion formulas are derived from the dispersion of higher-order modes with the high-frequency approximation. The waveform of the example problems is simulated using the real-axis integral method. The data points on the dispersion curves are processed in the frequency domain using the wave-number method. These extracted data are then substituted into the derived formulas. The results verify that employing higher-order SH guided waves for the evaluation of thickness and shear wave velocity yields less than1% error. This method can be applied to both metallic and non-metallic pipelines, thus opening new possibilities for health monitoring of pipeline structures.

Seabed structures and foundations related to deep-sea resource development:A review based on design and research

The deep‐sea ground contains a huge amount of energy and mineral resources,for example,oil,gas,and minerals.Various infrastructures such as floating structures,seabed structures,and foundations have been developed to exploit these resources.The seabed structures and foundations can be mainly classified into three types:subsea production structures,offshore pipelines,and anchors.This study reviewed the development,installation,and operation of these infrastructures,including their structures,design,installation,marine environment loads,and applications.On this basis,the research gaps and further research directions were explored through this literature review.First,different floating structures were briefly analyzed and reviewed to introduce the design requirements of the seabed structures and foundations.Second,the subsea production structures,including subsea manifolds and their foundations,were reviewed and discussed.Third,the basic characteristics and design methods of deep‐sea pipelines,including subsea pipelines and risers,were analyzed and reviewed.Finally,the installation and bearing capacity of deep‐sea subsea anchors and seabed trench influence on the anchor were reviewed.Through the review,it was found that marine environment conditions are the key inputs for any offshore structure design.The fabrication,installation,and operation of infrastructures should carefully consider the marine loads and geological conditions.Different structures have their own mechanical problems.The fatigue and stability of pipelines mainly depend on the soil‐structure interaction.Anchor selection should consider soil types and possible trench formation.These focuses and research gaps can provide a helpful guide on further research,installation,and operation of deep‐sea structures and foundations.

Analysis of faulting destruction and water supply pipeline damage from the first mainshock of the February 6,2023 Türkiye earthquake doublet

In 2023,two consecutive earthquakes exceeding a magnitude of 7 occurred in Türkiye,causing severe casualties and economic losses.The damage to critical urban infrastructure and building structures,including highways,railroads,and water supply pipelines,was particularly severe in areas where these structures intersected the seismogenic fault.Critical infrastructure projects that traverse active faults are susceptible to the influence of fault movement,pulse velocity,and ground motions.In this study,we used a unique approach to analyze the acceleration records obtained from the seismic station array(9 strong ground motion stations)located along the East Anatolian Fault(the seismogenic fault of the MW7.8 mainshock of the 2023 Türkiye earthquake doublet).The acceleration records were filtered and integrated to obtain the velocity and displacement time histories.We used the results of an on-site investigation,jointly conducted by China Earthquake Administration and Türkiye’s AFAD,to analyze the distribution of PGA,PGV,and PGD recorded by the strong motion array of the East Anatolian Fault.We found that the maximum horizontal PGA in this earthquake was 3.0 g,and the maximum co-seismic surface displacement caused by the East Anatolian Fault rupture was 6.50 m.As the fault rupture propagated southwest,the velocity pulse caused by the directional effect of the rupture increased gradually,with the maximum PGA reaching 162.3 cm/s.We also discussed the seismic safety of critical infrastructure projects traversing active faults,using two case studies of water supply pipelines in Türkiye that were damaged by earthquakes.We used a three-dimensional finite element model of the PE(polyethylene)water pipeline at the Islahiye State Hospital and fault displacement observations obtained through on-site investigation to analyze pipeline failure mechanisms.We further investigated the effect of the fault-crossing angle on seismic safety of a pipeline,based on our analysis and the failure performance of the large-diameter Thames Water pipeline during the 1999 Kocaeli earthquake.The seismic method of buried pipelines crossing the fault was summarized.

Numerical study on local scour characteristics around submarine pipelines in the Yellow River Delta silty sandy soil under waves and currents

Due to their high reliability and cost-efficiency,submarine pipelines are widely used in offshore oil and gas resource engineering.Due to the interaction of waves,currents,seabed,and pipeline structures,the soil around submarine pipelines is prone to local scour,severely affecting their operational safety.With the Yellow River Delta as the research area and based on the renormalized group(RNG)k-εturbulence model and Stokes fifth-order wave theory,this study solves the Navier-Stokes(N-S)equation using the finite difference method.The volume of fluid(VOF)method is used to describe the fluid-free surface,and a threedimensional numerical model of currents and waves-submarine pipeline-silty sandy seabed is established.The rationality of the numerical model is verified using a self-built waveflow flume.On this basis,in this study,the local scour development and characteristics of submarine pipelines in the Yellow River Delta silty sandy seabed in the prototype environment are explored and the influence of the presence of pipelines on hydrodynamic features such as surrounding flow field,shear stress,and turbulence intensity is analyzed.The results indicate that(1)local scour around submarine pipelines can be divided into three stages:rapid scour,slow scour,and stable scour.The maximum scour depth occurs directly below the pipeline,and the shape of the scour pits is asymmetric.(2)As the water depth decreases and the pipeline suspension height increases,the scour becomes more intense.(3)When currents go through a pipeline,a clear stagnation point is formed in front of the pipeline,and the flow velocity is positively correlated with the depth of scour.This study can provide a valuable reference for the protection of submarine pipelines in this area.

Pipeline血流导向装置治疗复杂性颅内动脉瘤预后的影响因素及列线图预测模型构建

目的 探讨Pipeline血流导向装置(PED)治疗复杂性颅内动脉瘤预后的影响因素。方法选择2021年1月至2023年4月安岳县人民医院和桂林医学院第二附属医院接诊的复杂性颅内动脉瘤患者98例。患者入组后均行PED治疗,收集可能影响复杂性颅内动脉瘤预后的影响因素。据改良Rankin量表得分将患者分为2组,≤2分为预后良好组,>2分为预后不良组,比较2组的临床资料。建立Nomograms模型并对模型进行验证。结果 98例患者中,10例(10.20%)出现预后不良。预后不良组与预后良好组患者年龄、高血压病史、糖尿病史、氯吡格雷抵抗、Fisher分级、动脉瘤多次破裂、动脉瘤位置、瘤体大小、瘤颈、多发及入院时Hunt-Hess分级差异均有统计学意义(P<0.05)。多因素分析结果显示,高血压病史、氯吡格雷抵抗、动脉瘤多次破裂、动脉瘤位置、多发及入院时Hunt-Hess分级为PED治疗复杂性颅内动脉瘤预后的独立性影响因素。Nomograms模型预测PED治疗复杂性颅内动脉瘤预后的AUC为0.849(95%CI:0.758~0.939)。模型组与验证组预测曲线与标准曲线基本拟合。决策曲线分析结果显示,当Nomograms模型预测PED治疗复杂性颅内动脉瘤预后不良的概率阈值为0.10~0.90时,患者的净受益率大于0。结论 PED治疗复杂性颅内动脉瘤预后不良的影响因素主要有高血压病史、氯吡格雷抵抗、动脉瘤多次破裂等,Nomograms模型可预测PED治疗复杂性颅内动脉瘤预后不良风险。