A high performance quadrature voltage-controlled oscillator (QVCO) is presented. It has been fabricated in SMIC 0.18 μm CMOS technology with top thick metal. The proposed QVCO employed cascade serial coupling for i...A high performance quadrature voltage-controlled oscillator (QVCO) is presented. It has been fabricated in SMIC 0.18 μm CMOS technology with top thick metal. The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation. Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise. A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO. The measured phase noise of the proposed QVCO achieves phase noise of-123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz, while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply. The QVCO can operate from 4.09 to 4.87 GHz (17.5%). Measured tuning gain of the QVCO (Kvco) spans from 44.5 to 66.7 MHz/V. The chip area excluding the pads and ESD protection circuit is 0.41 mm2.展开更多
A wide band, injection-coupled LC quadrature voltage control oscillator is presented. In the proposed circuit, two oscillators are injection locked by coupling their second-order harmonics in anti-phase, forcing the o...A wide band, injection-coupled LC quadrature voltage control oscillator is presented. In the proposed circuit, two oscillators are injection locked by coupling their second-order harmonics in anti-phase, forcing the outputs of two oscillators into a quadrature phase state. As the common-mode point sampling the second har- monic frequency, flicker noise of the tail current is suppressed, the phase noise is reduced .The proposed design accomplishes a wide tuning frequency range by a combination of using a 5-bit switch capacitor array (SCA) for discrete tuning in addition to linearly varying AMOS varactors for continuous tuning. The proposed design has been fabricated and verified in a 0.18/zm TSMC CMOS technology process. The measurement indicates that the quadrature voltage controlled oscillator has a 41.7% tuning range from 3.53 to 5.39 GHz. The measured phase noise is 127.98 dBc/Hz at 1 MHz offset at a 1.8 V supply voltage with a power consumption of 12 mW at a carrier frequency of 4.85 GHz.展开更多
A novel integrated quadrature voltage controlled oscillator (QVCO) with a feedback current source is presented in this paper. Benefiting from the current adjusting function of the feedback current source, the propos...A novel integrated quadrature voltage controlled oscillator (QVCO) with a feedback current source is presented in this paper. Benefiting from the current adjusting function of the feedback current source, the proposed QVCO exhibits a uniform phase noise over the entire tuning range. This QVCO is implemented in 65-nm CMOS technology. The measurement results show that it draws less than 3-mA average current from a 1.2-V supply and the phase noise is less than -110 dBc/Hz @IMHz offset over the entire tuning range. The fluctuation of phase noise @IMHz offset from the center frequency of 2.84-GHz to 3.27-GHz is less than 1 dBc/Hz, which validates the correctness of the proposed current source feedback technique.展开更多
This paper presents a low phase noise and low reference spur quadrature phase-locked loop (QPLL) circuit that is implemented as a part ofa fi'equency synthesizer for China UWB standard systems. A glitch-suppressed ...This paper presents a low phase noise and low reference spur quadrature phase-locked loop (QPLL) circuit that is implemented as a part ofa fi'equency synthesizer for China UWB standard systems. A glitch-suppressed charge pump (CP) is employed for reference spur reduction. By forcing the phase frequency detector and CP to operate in a linear region of its transfer function, the linearity of the QPLL is further improved. With the proposed series-quadrature voltage-controlled oscillator, the phase accuracy of the QPLL is guaranteed. The circuit is fab- ricated in the TSMC 0.13/Jm CMOS process and operated at 1.2-V supply voltage. The QPLL measures a phase noise of -95 dBc/Hz at 100-kHz offset and a reference spur of-71 dBc. The fully-integrated QPLL dissipates a current of 13 mA.展开更多
This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44...This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than -60 dBc. The settling time is within 80°s. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.展开更多
A 25 Gbit/s clock and data recovery (CDR) circuit with 1:2 demultiplexer for 100 Gbit/s Ethemet (100 GbE) optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company (TSMC...A 25 Gbit/s clock and data recovery (CDR) circuit with 1:2 demultiplexer for 100 Gbit/s Ethemet (100 GbE) optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company (TSMC) 65nm complementary metal-oxide-semiconductor (CMOS) technology. A novel quadrature voltage-controlled-oscillator (QVCO) structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array to sample the 25 Gbit/s input data and align the data phase, so the 25 Gbit/s data are retimed and demultiplexed into two paths 12.5 Gbit/s output data. Experimental results show that the recovered clock exhibits a peak-to-peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to 231 - 1 pseudorandom bit sequence (PRBS) input. For 1.2 V voltage supply, the CDR circuit consumes 92 mW (excluding output buffers).展开更多
基金supported by the Ministry of Industry and Information Technology of China(No.2009ZX03006-009)
文摘A high performance quadrature voltage-controlled oscillator (QVCO) is presented. It has been fabricated in SMIC 0.18 μm CMOS technology with top thick metal. The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation. Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise. A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO. The measured phase noise of the proposed QVCO achieves phase noise of-123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz, while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply. The QVCO can operate from 4.09 to 4.87 GHz (17.5%). Measured tuning gain of the QVCO (Kvco) spans from 44.5 to 66.7 MHz/V. The chip area excluding the pads and ESD protection circuit is 0.41 mm2.
基金supporteded by the National Natural Science Foundation of China(No.41274047)the Guangdong Province Science and Technology Program(No.2013B090500049)
文摘A wide band, injection-coupled LC quadrature voltage control oscillator is presented. In the proposed circuit, two oscillators are injection locked by coupling their second-order harmonics in anti-phase, forcing the outputs of two oscillators into a quadrature phase state. As the common-mode point sampling the second har- monic frequency, flicker noise of the tail current is suppressed, the phase noise is reduced .The proposed design accomplishes a wide tuning frequency range by a combination of using a 5-bit switch capacitor array (SCA) for discrete tuning in addition to linearly varying AMOS varactors for continuous tuning. The proposed design has been fabricated and verified in a 0.18/zm TSMC CMOS technology process. The measurement indicates that the quadrature voltage controlled oscillator has a 41.7% tuning range from 3.53 to 5.39 GHz. The measured phase noise is 127.98 dBc/Hz at 1 MHz offset at a 1.8 V supply voltage with a power consumption of 12 mW at a carrier frequency of 4.85 GHz.
文摘A novel integrated quadrature voltage controlled oscillator (QVCO) with a feedback current source is presented in this paper. Benefiting from the current adjusting function of the feedback current source, the proposed QVCO exhibits a uniform phase noise over the entire tuning range. This QVCO is implemented in 65-nm CMOS technology. The measurement results show that it draws less than 3-mA average current from a 1.2-V supply and the phase noise is less than -110 dBc/Hz @IMHz offset over the entire tuning range. The fluctuation of phase noise @IMHz offset from the center frequency of 2.84-GHz to 3.27-GHz is less than 1 dBc/Hz, which validates the correctness of the proposed current source feedback technique.
基金supported by the National Science & Technology Major Projects of China(Nos.2009ZX03006-007-01,2009ZX03007-001, 2009ZX03006-009)the National High Tech R&D Program of China(No.2009AA01Z261 )
文摘This paper presents a low phase noise and low reference spur quadrature phase-locked loop (QPLL) circuit that is implemented as a part ofa fi'equency synthesizer for China UWB standard systems. A glitch-suppressed charge pump (CP) is employed for reference spur reduction. By forcing the phase frequency detector and CP to operate in a linear region of its transfer function, the linearity of the QPLL is further improved. With the proposed series-quadrature voltage-controlled oscillator, the phase accuracy of the QPLL is guaranteed. The circuit is fab- ricated in the TSMC 0.13/Jm CMOS process and operated at 1.2-V supply voltage. The QPLL measures a phase noise of -95 dBc/Hz at 100-kHz offset and a reference spur of-71 dBc. The fully-integrated QPLL dissipates a current of 13 mA.
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z2b2).
文摘This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver. Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output. Measured spurious tones are lower than -60 dBc. The settling time is within 80°s. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.
基金supported by the Communication Systems Project of Jiangsu Department (JHB04010)the National Natural Science Foundation of China (60976029)
文摘A 25 Gbit/s clock and data recovery (CDR) circuit with 1:2 demultiplexer for 100 Gbit/s Ethemet (100 GbE) optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company (TSMC) 65nm complementary metal-oxide-semiconductor (CMOS) technology. A novel quadrature voltage-controlled-oscillator (QVCO) structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array to sample the 25 Gbit/s input data and align the data phase, so the 25 Gbit/s data are retimed and demultiplexed into two paths 12.5 Gbit/s output data. Experimental results show that the recovered clock exhibits a peak-to-peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to 231 - 1 pseudorandom bit sequence (PRBS) input. For 1.2 V voltage supply, the CDR circuit consumes 92 mW (excluding output buffers).