This paper introduces a 2.5GHz low phase-noise cross-coupled LC-VCO realized in 0.35μm SiGe BiCMOS technology. The conventional definition of a VCO operating regime is revised from a new perspective. Analysis shows t...This paper introduces a 2.5GHz low phase-noise cross-coupled LC-VCO realized in 0.35μm SiGe BiCMOS technology. The conventional definition of a VCO operating regime is revised from a new perspective. Analysis shows the importance of inductance and bias current selection for oscillator phase noise optimization. Differences between CMOS and BJT VCO design strategy are then analyzed and the conclusions are summarized. In this implementation, bonding wires form the resonator to improve the phase noise performance. The VCO is then integrated with other components to form a PLL frequency synthesizer with a loop bandwidth of 30kHz. Measurement shows a phase noise of - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from a 2.5GHz carrier. At a supply voltage of 3V, the VCO core consumes 8mA. To our knowledge,this is the first differential cross-coupled VCO in SiGe BiCMOS technology in China.展开更多
An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise...An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise performance has been realized. All the building blocks are implemented with differential topology except for the off-chip loop filter. To further reduce the phase noise,bonding wires are used to form the resonator in the LC-VCO. The frequency synthesizer operates from 2.39 to 2.72GHz with output power of about 0dBm. The measured closed-loop phase noise is - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from the carrier. The power level of the reference spur is less than - 72dBc. With a 3V power supply, the whole chip including the output buffers consumes 60mA.展开更多
An open-loop 20 GSps track-and-hold amplifier （THA） using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to a...An open-loop 20 GSps track-and-hold amplifier （THA） using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to achieve high speed and good linearity. A cross-coupled pair is used in the input buffer to suppress the charge injection and clock feedthrough. Both the input and output buffers use an active inductor load to achieve high signal bandwidth. The THA is realized with 0.18/zm SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply and with a core area of 0.024 mme. The measurement results show that the SFDR is 32.4 dB with a 4 GHz sine wave input at a 20 GSps sampling rate, and the third harmonic distortion is -48 dBc. The effective resolution bandwidth of the THA is 12 GHz and the figure of merit is only 0.028 mW/GHz.展开更多
This paper presents a 2.4 GHz power amplifier （PA） designed and implemented in 0.35μm SiGe BiCMOS technology. Instead of chip grounding through PCB vias, a metal plate with a mesa connecting ground is designed to d...This paper presents a 2.4 GHz power amplifier （PA） designed and implemented in 0.35μm SiGe BiCMOS technology. Instead of chip grounding through PCB vias, a metal plate with a mesa connecting ground is designed to decrease the parasitics in the PCB, improving the stability and the gain of the circuit. In addition, a low-pass network for output matching is designed to improve the linearity and power capability. At 2.4 GHz, a P1dB of 15.7 dBm has been measured, and the small signal gain is 27.6 dB with S11 〈 -7 dB and S22 〈 -15 dB.展开更多
This paper presents the circuit design and measured performance of a multi-band tuner for mobile TV applications. The tuner RFIC is composed of a wideband front-end, an analog baseband, a full integrated fractional- N...This paper presents the circuit design and measured performance of a multi-band tuner for mobile TV applications. The tuner RFIC is composed of a wideband front-end, an analog baseband, a full integrated fractional- N synthesizer and an Iac digital interface. To meet the stringent adjacent channel rejection （ACR） requirements of mobile TV standards while keeping low power consumption and low cost, direct conversion architecture with a local AGC scheme is adopted in this design. Eighth-order elliptic active-RC filters with large stop band attenuation and a sharp transition band are chosen as the channel select filter to further improve the ACR preference. The chip is fabricated in a 0.35-#m SiGe BiCMOS technology and occupies a silicon area of 5.5 mm2. It draws 50 mA current from a 3.0 V power supply. In CMMB application, it achieves a sensitivity of-97 dBm with 1/2 coding QPSK signal input and over 40 dB ACR.展开更多
A 23 GHz voltage controlled oscillator （VCO） with very low power consumption is presented. This paper presents the design and measurement of an integrated millimeter wave VCO. This VCO employs an on-chip inductor an...A 23 GHz voltage controlled oscillator （VCO） with very low power consumption is presented. This paper presents the design and measurement of an integrated millimeter wave VCO. This VCO employs an on-chip inductor and MOS varactor to form a high Q resonator. The VCO RFIC was implemented in a 0.18 #m 120 GHz ft SiGe hetero-junction bipolar transistor （HBT） BiCMOS technology. The VCO oscillation frequency is around 23 GHz, targeting at the ultra wideband （UWB） and short range radar applications. The core of the VCO circuit consumes 1 mA current from a 2.5 V power supply and the VCO phase noise was measured at around -94 dBc/Hz at a 1 MHz frequency offset. The FOM of the VCO is -177 dBc/Hz.展开更多
A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is cho...A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.展开更多
文摘This paper introduces a 2.5GHz low phase-noise cross-coupled LC-VCO realized in 0.35μm SiGe BiCMOS technology. The conventional definition of a VCO operating regime is revised from a new perspective. Analysis shows the importance of inductance and bias current selection for oscillator phase noise optimization. Differences between CMOS and BJT VCO design strategy are then analyzed and the conclusions are summarized. In this implementation, bonding wires form the resonator to improve the phase noise performance. The VCO is then integrated with other components to form a PLL frequency synthesizer with a loop bandwidth of 30kHz. Measurement shows a phase noise of - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from a 2.5GHz carrier. At a supply voltage of 3V, the VCO core consumes 8mA. To our knowledge,this is the first differential cross-coupled VCO in SiGe BiCMOS technology in China.
文摘An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise performance has been realized. All the building blocks are implemented with differential topology except for the off-chip loop filter. To further reduce the phase noise,bonding wires are used to form the resonator in the LC-VCO. The frequency synthesizer operates from 2.39 to 2.72GHz with output power of about 0dBm. The measured closed-loop phase noise is - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from the carrier. The power level of the reference spur is less than - 72dBc. With a 3V power supply, the whole chip including the output buffers consumes 60mA.
基金supported by the PhD Programs Foundation of Ministry of Education of China(No.2009009211001)the Important National Science&Technology Specific Projects(No.2010ZX03006-003-02)
文摘An open-loop 20 GSps track-and-hold amplifier （THA） using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to achieve high speed and good linearity. A cross-coupled pair is used in the input buffer to suppress the charge injection and clock feedthrough. Both the input and output buffers use an active inductor load to achieve high signal bandwidth. The THA is realized with 0.18/zm SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply and with a core area of 0.024 mme. The measurement results show that the SFDR is 32.4 dB with a 4 GHz sine wave input at a 20 GSps sampling rate, and the third harmonic distortion is -48 dBc. The effective resolution bandwidth of the THA is 12 GHz and the figure of merit is only 0.028 mW/GHz.
文摘This paper presents a 2.4 GHz power amplifier （PA） designed and implemented in 0.35μm SiGe BiCMOS technology. Instead of chip grounding through PCB vias, a metal plate with a mesa connecting ground is designed to decrease the parasitics in the PCB, improving the stability and the gain of the circuit. In addition, a low-pass network for output matching is designed to improve the linearity and power capability. At 2.4 GHz, a P1dB of 15.7 dBm has been measured, and the small signal gain is 27.6 dB with S11 〈 -7 dB and S22 〈 -15 dB.
文摘This paper presents the circuit design and measured performance of a multi-band tuner for mobile TV applications. The tuner RFIC is composed of a wideband front-end, an analog baseband, a full integrated fractional- N synthesizer and an Iac digital interface. To meet the stringent adjacent channel rejection （ACR） requirements of mobile TV standards while keeping low power consumption and low cost, direct conversion architecture with a local AGC scheme is adopted in this design. Eighth-order elliptic active-RC filters with large stop band attenuation and a sharp transition band are chosen as the channel select filter to further improve the ACR preference. The chip is fabricated in a 0.35-#m SiGe BiCMOS technology and occupies a silicon area of 5.5 mm2. It draws 50 mA current from a 3.0 V power supply. In CMMB application, it achieves a sensitivity of-97 dBm with 1/2 coding QPSK signal input and over 40 dB ACR.
基金Project supported by the State Key Development Program for Basic Research of China(No.2010CB327502)
文摘A 23 GHz voltage controlled oscillator （VCO） with very low power consumption is presented. This paper presents the design and measurement of an integrated millimeter wave VCO. This VCO employs an on-chip inductor and MOS varactor to form a high Q resonator. The VCO RFIC was implemented in a 0.18 #m 120 GHz ft SiGe hetero-junction bipolar transistor （HBT） BiCMOS technology. The VCO oscillation frequency is around 23 GHz, targeting at the ultra wideband （UWB） and short range radar applications. The core of the VCO circuit consumes 1 mA current from a 2.5 V power supply and the VCO phase noise was measured at around -94 dBc/Hz at a 1 MHz frequency offset. The FOM of the VCO is -177 dBc/Hz.
基金Supported by the National Natural Science Foundation of China(No.61534003)
文摘A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.
