一种具有1~128倍可变增益放大器的低功耗Sigma⁃Delta ADC

为满足传感器应用的低功耗需求,设计并实现了一种低功耗Sigma⁃Delta模数转换器(ADC)芯片。该ADC采用一阶全差分开关电容Sigma⁃Delta调制器,且集成了可编程增益放大器(PGA)和Bandgap;使用1.5 bit量化结构,相较于1 bit量化结构减小了3 dB的量化误差;使用优化的反馈电路,减小了电容失配引入的误差;PGA采用轨到轨的运放电路拓扑,增大了整个芯片的电压适应范围。基于180 nm CMOS工艺对该ADC进行了设计和流片。测试结果表明:该Sigma⁃Delta ADC在采样频率512 kHz、过采样率(OSR)为256时,峰值信噪谐波失真比(SNDR)和有效位数(ENOB)分别为75.29 dB和12.21 bit,芯片功耗仅为0.92 mW。芯片能在2.3~5.5 V宽电源电压范围内正常工作,可实现最大128 V/V的增益。适用于小型传感器的信号测量应用,可以满足小型传感器低功耗、高精度的需求。

一种应用于物联网传感器的伪三阶Delta-Sigma调制器

针对物联网传感器难以同时满足高分辨率与低功耗的瓶颈问题,本文设计了一种伪三阶离散时间delta-sigma调制器.该架构将一阶无源噪声整形SAR(Successive Approximation Register)量化器嵌入传统二阶delta-sigma调制器以实现更强的噪声整形能力.本文设计允许系统在更低的过采样率(Over Sampling Ratio,OSR)下获取更高的峰值SQNR(Signal-to-Quantizing Noise Ratio),有效缓解了系统精度和功耗之间的设计矛盾,并且减少了有源积分器的使用.针对传统有源加法器高功耗和无源加法器存在衰减不确定性的问题,本文提出了一种新型前馈求和量化电路,它具有对衰减不敏感的优势并且降低了第二级有源积分器的驱动压力,这进一步降低了系统的功耗.本文提出的delta-sigma调制器采用180 nm CMOS(Complementary Metal Oxide Semiconductor)工艺制造并测试.在电源电压1.4 V下,芯片测试功耗为47.2μW.在带宽为8 kHz的测试条件下,调制器的DR(Dynamic Range)、峰值SNDR(Signal-to-Noise and Distortion Ratio)和SFDR(Spurious-Free Dynamic Range)分别为97.2 dB,96.6 dB和114.4 dB.因此,Schreier和Walden的SNDR FoM(Figure of Merit)优值达到了178.9 dB和0.053 pJ/step.本文提出的伪三阶delta-sigma调制器在功耗和分辨率之间实现了较好的权衡,为物联网领域的低功耗高分辨率调制器设计提供了较好的解决方案.

一种高精度音频Sigma-Delta DAC的设计

设计了一种应用于音频Codec的高精度Sigma-Delta DAC,针对数字插值滤波器占用面积大的问题,提出了乘法器复用的方法,减少数字电路的硬件消耗。为解决Sigma-Delta调制器多比特量化引起的非线性问题,引入DWA(Data Weight Average)算法,提高系统的精度。此外,DCT(Direct Charge Transfer)电路用于实现数字域到模拟域的高精度转换。电路采用0.18μm CMOS工艺,整体DAC的信噪比为105.7dB@1150Hz,有效位数达到17.26bit。

高精度Sigma-Delta调制器设计

近年来,在过采样型模数转换器中,Sigma-Delta模数转换器以其较高的精度成为模数转换器的热点。介绍了一种高精度低功耗的Sigma-Delta调制器设计。使用Matlab工具完成三阶一位量化CIFF结构的系统仿真,在系统级仿真结果的指导下,积分器采用分级结构优化电路结构。积分器电路模块设计采用了全差分式开关电容电路,抑制了谐波失真对输出精度的影响。仿真结果显示:5 S/s挡位时,对应的PVT组合中最低有效位数为17.67 bits;2 kS/s挡位时,对应的PVT组合中最低有效位数为15.89 bits,整个调制器功耗低于3 mW。通过改进调制器整体架构、积分器结构和量化器的设计方法,降低了调制器功耗,提升了调制器精度。

基于扰动Delta-sigma调制器的小数分频器

文中基于扰动Delta-sigma调制器分析并设计了一款动态分频比控制的宽带小数分频器链路。其中,整数分频器链路由高速2分频器和7级2/3分频器链路级联构成,小数控制部分由外加扰动的Delta-sigma调制器构成。通过理论分析和仿真表明,合理选择扰动信号的添加位置,可以有效延长Delta-sigma调制器的输出序列长度,从而平滑Delta-sigma调制器的输出频谱。该分频器电路采用TPS 65 nm射频绝缘体上硅(RFSOI)互补金属氧化物半导体(CMOS)工艺制造,包括焊盘在内的芯片面积为0.57 mm 2。测试结果表明,该小数分频器链路在1.2 V的供电电压下,最大工作电流为22.2 mA,可以在9 GHz~20 GHz的输入频率下动态加载控制字并实现小数分频功能。

采用Mash2-1架构的高精度Sigma-Delta ADC设计

鉴于模数转换器(ADC)在芯片和混合信号处理领域举足轻重的作用,为探索进一步提高模数转换器精度的可能性,满足当今应用系统对模数转换精度的新需求,设计一款基于Mash2-1级联架构的sigma-delta ADC。设计采用TSMC 180 nm CMOS工艺,在完成调制器电路的同时,使用Verilog代码方式实现了配套的误差消除以及数字抽取滤波器。对调制器进行了建模及非理想因素的分析,并通过使用斩波调制技术等手段对电路的非理想性进行优化。经仿真验证,结果表明,本设计在3.3 V电源、27℃工作环境、TT典型工艺条件下,表现出优异的信噪比,总谐波失真等性能指标也较理想,适用于高精度、低失真的应用场合。

一种高性能、小面积的Sigma Delta DAC数字电路设计

该文设计一种高性能、小面积的Sigma Delta DAC,其中包括插值滤波器和数字调制器。插值滤波器由两级半带滤波器和CIC滤波器级联组成,实现128倍插值。在两级半带滤波器硬件实现中,滤波器系数采用查找表实现,滤波运算数据采用SRAM存储,并通过乘法器的时分复用实现,大大减少对硬件资源的使用。数字调制器采用量化误差反馈型的多bit量化Mash 1-1-1结构,这种结构不需要复杂的乘法运算,简化设计并提高系统的可靠性。该DAC数字电路在90 nm CMOS工艺下实现,面积为0.0535 mm^(2),功耗为1.0103 mW。经过测试,数字调制器输出的带内信噪比为132.2 dB,有效位数21.67,可以满足小面积、高性能DAC的设计需求。

高精度音频Sigma-Delta调制器综述

Sigma-Delta(Σ-Δ)模数转换器(ADC)基于过采样和噪声整形技术,可实现高分辨率,具有无源器件匹配性要求低、结构简单等特点。在高精度音频领域,Σ-ΔADC能够实现高动态范围和良好的功率效率得到了广泛的关注和应用。近年来,依托先进工艺、先进技术进行低功耗高精度的音频ADC的设计已经成为新的研究热点。然而随着工艺技术向低节点的持续发展、电源电压的不断降低,使得Σ-ΔADC的电路设计更具挑战性。该文对高精度音频Sigma-Delta调制器的离散型设计、连续型设计的研究现状进行综述,为高精度音频Sigma-Delta调制器设计提供理论支撑,并给出研究前景展望。

基于参考电压修正的双级矩阵变换器Delta-Sigma调制

Delta-Sigma调制(DSM)可在无需随机过程统计特性和复杂谐波理论分析的基础上,依托其过采样特性实现电力电子变换器变频调制。双级矩阵变换器(TSMC)作为一种理想的“全硅”交-交变换器,若能够将DSM引入TSMC,可进一步优化其电磁干扰(EMI)水平和运行效率,但TSMC的直流链电压波动问题导致TSMC-DSM策略难以直接实现。针对TSMC-DSM实现问题,该文提出一种基于参考电压修正的DSM策略。在所提方法中,通过解析TSMC整流级调制过程,将逆变级参考电压按照整流级矢量作用顺序进行修正,并依次获得各扇区参考电压修正系数。最后,在两相坐标系下分别构建两个DSM调制器,并将修正后的逆变级电压参考值引入DSM调制器以实现高性能TSMC-DSM策略。实验结果表明,所提策略能够对输出电压、电流频谱进行合理整形以减少系统对外部的电磁干扰,同时具备优良的电压传输比和动态调制性能。

一种sigma-delta ADC数字抽取滤波器设计与实现

数字滤波器是sigma-delta模数转换器的主要组成部分,用于对调制器输出信号的滤波和抽取。本文设计的数字滤波器是由间接型级联积分梳状滤波器组成。在说明CIC滤波器原理的基础上,通过Verilog实现并验证其功能与性能。

An 18-bit sigma–delta switched-capacitor modulator using 4-order single-loop CIFB architecture

Oversampling sigma–delta(Σ–Δ)analog-to-digital converters(ADCs)are currently one of the most widely used architectures for high-resolution ADCs.The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed.Structurally,theΣ–ΔADC is divided into two parts:a front-end analog modulator and a back-end digital filter.The performance of the front-end analog modulator has a marked influence on the entireΣ–ΔADC system.In this paper,a 4-order single-loop switched-capacitor modulator with a CIFB(cascade-of-integrators feed-back)structure is proposed.Based on the chosen modulator architecture,the ASIC circuit is implemented using a chartered 0.35μm CMOS process with a chip area of 1.72×0.75 mm^2.The chip operates with a 3.3-V power supply and a power dissipation of 22 mW.According to the results,the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits(ENOB)was almost 18-bit.

Chip Design of a Low-Voltage Wideband Continuous-Time Sigma-Delta Modulator with DWA Technology for WiMAX Applications

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.

Improved time-interleaved error feedback delta sigma modulator for digital transmitter application

Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.

A New Approach to Complex Bandpass Sigma Delta Modulator Design for GPS/Galileo Receiver

In this paper, new complex band pass filter architecture for continuous time complex band pass sigma delta modulator is presented. In continuation of paper the modulator is designed for GPS and Galileo receiver. This modulator was simulated in standard 0.18 μm CMOS TSMC technology and has bandwidth of 2MHz and 4MHz for GPS and Galileo centered in 4.092 MHz. The dynamic range (DR) is 56.5/49 dB (GPS/Galileo) at sampling rate of 125 MHz. The modulator has power consumption of 4.1 mw with 3 V supply voltage.

A new digital transmitter based on delta sigma modulator with bus-splitting

A new digital transmitter based on delta sigma modulator( DSM) with bus-splitting is presented in this paper. The second order low pass error-feedback delta sigma modulator( EF-DSM) is focused. The signal to noise ratio( SNR) of the EF-DSM is derived for different bus-splitting bits.Following the EF-DSM,a multi-bit digital up mixer is used for carrier frequency transform. In order to validate the theory of bus-splitting,two types of transmitters are implemented on FPGA for comparison,in which one is with non-bus-splitting and the other is with bus-splitting. The FPGA implemented transmitter with bus-splitting promotes the maximum operation speed by 39%,and reduces hardware consumptions more than 16%. Both single tone and orthogonal frequency division multiplexing( OFDM) signal source are used to evaluate the proposed transmitter.

A Novel Full Differential Feedforward Fourth-Order Bandpass Sigma-Delta Modulator

In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modulator was proposed. It used a resonator based on Salo architecture,which employed doublesampling and double-delay technique. The results show that the proposed modulator can achieve lower power consumption and a lower capacitive load than the conventional bandpass modulators on the platform of Simulink. The circuit is implemented with TSMC0. 18 μm CMOS process and operates at a sampling frequency of 20 MHz, 80 MHz effective sampling frequency. Furthermore,it consumes 21. 2 mW from a 1. 8 V supply. The simulated peak signal-to-noise ratio( SNR) is 85. 9 dB and the dynamic range( DR) is 91 dB with 200 kHz bandwidth.

FPGA implementation of bit-stream neuron and perceptron based on sigma delta modulation

To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.

基于Sigma-Delta AD采样的双向有源桥变换器中变压器的直流偏置抑制

双有源桥(DAB)变换器兼具高效和高功率密度,且其能量可双向流动,从而得到广泛应用。DAB变换器易因电路参数、驱动信号不对称等因素造成磁不平衡,进而影响电路正常稳定工作。因此,设计了一种变压器绕组的直流偏置电流检测控制策略。该策略通过采样电阻和delta-sigma(Δ-Σ)调制将电流转换为1位数据流,采样电阻放置在H桥直流端,可分别获得绕组正半周和负半周中电流平均值,相减可得绕组电流直流分量。同时,设计了一种DAB的直流电流抑制方法,通过设计控制器以实现微调任一桥臂的占空比来调节H桥输出电压的直流分量。最后,通过Matlab仿真验证了直流偏置电流检测与控制策略的有效性。

一种高精度高信噪比的Sigma-Delta调制器设计

为满足模数转换器设计和应用中系统对精度日益增长的高要求,提出一种高精度高信噪比的Sigma-Delta调制器。Sigma-Delta调制器采用三阶CIFB架构,同时在第一级放大器部分设置斩波电路,以此提高信噪比。采用TSMC 180 nm CMOS工艺进行设计并通过仿真验证。仿真结果表明,在电源电压为3.3V,工作温度为27℃,工艺角为典型工艺角TT的情况下,Sigma-Delta调制器对于信噪比、有效位数等指标均有优秀的性能表现,适于高精度系统的应用场合。

参数自适应误差自校准的Sigma-Delta闭环微机械陀螺仪

提出并实现了一种用于MEMS谐振陀螺仪的新型自适应自校准多级噪声整形(MASH)微机电sigma-delta闭环测控电路方案。该技术针对高精度MEMS音叉陀螺仪的误差校准,开发了在线自适应误差校准的MASH2-0闭环测控电路,且无需使用任何额外的机械校准方法。该技术不仅可以有效地消除由于MEMS音叉陀螺仪敏感元件加工误差和接口测控电路之间的参数失配在输出端产生的误差影响,并且能够校正由非理想信号传递函数而导致的信号链路传输中的频谱失真和增益失配。试验结果表明,与传统的闭环MEMS陀螺仪相比,所提出的自适应MASH2-0闭环测控电路技术可以实现更好的系统稳定性、动态范围和噪声性能。